可以指定要分配的引脚子集并让工具从中选择吗？

首先，我会说至少有一种方法可以做你所要求的，但不清楚你会从中获得任何好处。
您的假设是工具比为您的设计选择IO站点更好，而我很少发现情况就是如此。
但是如果你想尝试一下：
方法1）
LOC或PROHIBIT芯片的所有其他引脚。
固定在电路板设计中的LOC引脚。
禁止任何其他引脚，以防止它们被选择用于尚未定位的顶级信号。
您已经知道LOC语法。
检查约束指南以了解PROHIBIT语法。
方法2）
使用LOCATE而不是LOC将模块映射到站点组。
这在约束指南中描述了通常的“示例”风格，除非你已经掌握了这个概念，否则没什么意义。
即“示例”更像是语法的BNF定义，如果将它们粘贴到设计中，则会产生错误。
如果你能弄清楚如何使用这种方法，你将获得在这里发布你的UCF的荣誉。
-  Gabor
在原帖中查看解决方案



以下为原文

First, I'll say that there is at least one way to do what you're asking, but it's not clear that you'll get any benefit from it.  Your assumption is that the tools are better than you are at selecting IO sites for your design, while I've rarely found that to be the case.  But if you want to try it:
 
Method 1)
 
LOC or PROHIBIT all the other pins of the chip.  LOC pins that are fixed in your board design.  PROHIBIT any other pins to prevent them from being chosen for top level signals that haven't already been LOCed.  You already know the LOC syntax.  Check the Constraints Guide for the PROHIBIT syntax.
 
Method 2)
 
Use LOCATE rather than LOC to map a module to a site group.  This is described in the constraints guide with the usual style of "example" that makes little sense unless you already grasp the concept.  i.e. the "examples" are more like a BNF definition of the syntax and would create errors if you pasted them into a design.  If you can figure out how to use this method, you'll get kudos for posting your UCF here.
-- GaborView solution in original post

您应该始终锁定引脚分配。
您的PCB不会改变，因此您的引脚分配也不会改变。
----------------------------是的，我这样做是为了谋生。



以下为原文

You should ALWAYS lock down the pin assignments. Your PCB doesn't change, therefore neither can your pin assignments.
----------------------------Yes, I do this for a living.

啊，让我澄清一下。
我的PCB还有16个输入，来自外部板，因此我可以根据需要更改输入的分配。
更具体地说，我有一个带有32-SMA输出的16通道10 GHz多路分解器评估板。
这些都是我制作的PCB，它采用这些32-SMA输出并将它们路由到我的FPGA评估板所具有的Samtec接口。
因此，我可以自由地改变DMUX中的SMA电缆以满足我的需求。



以下为原文

Ah let me clarify. My PCB also has 16 inputs, which come from an external board, so I am able to change the assignment of the inputs as I need to.
 
More specifically, I have a 16-channel 10 GHz demultiplexer evaluation board with 32-SMA outputs. These go to a PCB that I have made, which takes these 32-SMA outputs and routes them into the Samtec interface my FPGA evaluation board has. So, I have the freedom to change around the SMA cables out of the DMUX to suit my needs.

kwiatlab写道：
啊，让我澄清一下。
我的PCB还有16个输入，来自外部板，因此我可以根据需要更改输入的分配。
更具体地说，我有一个带有32-SMA输出的16通道10 GHz多路分解器评估板。
这些都是我制作的PCB，它采用这些32-SMA输出并将它们路由到我的FPGA评估板所具有的Samtec接口。
因此，我可以自由地改变DMUX中的SMA电缆以满足我的需求。
那么，您需要知道使用了哪个输入，对吧？
并且您无法在配置后更改分配;
事实上，你不能在地方和路线后改变它！
所以再次，总是锁定您的引脚分配。
----------------------------是的，我这样做是为了谋生。



以下为原文

kwiatlab wrote:
Ah let me clarify. My PCB also has 16 inputs, which come from an external board, so I am able to change the assignment of the inputs as I need to.
 
More specifically, I have a 16-channel 10 GHz demultiplexer evaluation board with 32-SMA outputs. These go to a PCB that I have made, which takes these 32-SMA outputs and routes them into the Samtec interface my FPGA evaluation board has. So, I have the freedom to change around the SMA cables out of the DMUX to suit my needs.

Well, you need to know which input is used, right? And you can't change the assignment after configuration; indeed, you can't change it after place and route!
 
So again, ALWAYS lock down your pin assignments.
----------------------------Yes, I do this for a living.

首先，我会说至少有一种方法可以做你所要求的，但不清楚你会从中获得任何好处。
您的假设是工具比为您的设计选择IO站点更好，而我很少发现情况就是如此。
但是如果你想尝试一下：
方法1）
LOC或PROHIBIT芯片的所有其他引脚。
固定在电路板设计中的LOC引脚。
禁止任何其他引脚，以防止它们被选择用于尚未定位的顶级信号。
您已经知道LOC语法。
检查约束指南以了解PROHIBIT语法。
方法2）
使用LOCATE而不是LOC将模块映射到站点组。
这在约束指南中描述了通常的“示例”风格，除非你已经掌握了这个概念，否则没什么意义。
即“示例”更像是语法的BNF定义，如果将它们粘贴到设计中，则会产生错误。
如果你能弄清楚如何使用这种方法，你将获得在这里发布你的UCF的荣誉。
-  Gabor



以下为原文

First, I'll say that there is at least one way to do what you're asking, but it's not clear that you'll get any benefit from it.  Your assumption is that the tools are better than you are at selecting IO sites for your design, while I've rarely found that to be the case.  But if you want to try it:
 
Method 1)
 
LOC or PROHIBIT all the other pins of the chip.  LOC pins that are fixed in your board design.  PROHIBIT any other pins to prevent them from being chosen for top level signals that haven't already been LOCed.  You already know the LOC syntax.  Check the Constraints Guide for the PROHIBIT syntax.
 
Method 2)
 
Use LOCATE rather than LOC to map a module to a site group.  This is described in the constraints guide with the usual style of "example" that makes little sense unless you already grasp the concept.  i.e. the "examples" are more like a BNF definition of the syntax and would create errors if you pasted them into a design.  If you can figure out how to use this method, you'll get kudos for posting your UCF here.
-- Gabor

UCF约束语法支持LOC约束，并带有逗号分隔的值列表。
我不确定它是否适用于I / O引脚，但很可能。



以下为原文

The UCF constraint syntax supports LOC constraints with a comma seperated list of values. I'm not certain it works with I/O pins but it very well might.

LOCATE是一个PCF约束，通常不用作映射的输入源。
它可以完成，但它使流程复杂化。
确保用户约束位于原理图开始/原理图结束定义区域之外，否则将被地图覆盖。



以下为原文

LOCATE is a PCF constraint that's not normally used as an input source to map. It can be done but it complicates the flow. Make sure that the user constraint is outside the Schematic Start/Schematic End defined area or it will be overritten by map.