时钟垫驱动非缓冲基元，即使我有一个缓冲区

C，
在ucf文件中：
NET“clock_p”DIFF_TERM = TRUE; NET“clock_p”LOC = H14; NET“clock_n”DIFF_TERM = TRUE; NET“clock_n”LOC = H15;
然后在VHDL中，
port（clock_p，clock_n：在std_logic中;（等等，等等）
（声明接口......）
接着，
IBUFGDS_clock：IBUFGDS端口映射（O =>时钟， - 时钟缓冲输出I => clock_p， -  Diff_p时钟缓冲输入（连接到顶级端口）IB => clock_n  -  Diff_n时钟缓冲输入（直接连接到顶部）
-level port））;
在“开始”之后实例化（连接）时钟缓冲器，并将其连接到右侧引脚。
Austin Lesea主要工程师Xilinx San Jose
在原帖中查看解决方案



以下为原文

c,
 
In the ucf file:
 
NET "clock_p" DIFF_TERM = TRUE;
NET "clock_p" LOC=H14;
NET "clock_n" DIFF_TERM = TRUE;
NET "clock_n" LOC=H15;
 
And then in the VHDL,
 
port (          clock_p,clock_n : in std_logic;  (etc, etc, etc)


 (to declare the interfaces...)
 
and then,
 
IBUFGDS_clock : IBUFGDS
      port map (
     O => clock,  -- Clock buffer output
     I => clock_p,  -- Diff_p clock buffer input (connect to top-level port)
    IB => clock_n -- Diff_n clock buffer input (connect directly to top-level port)
      );


after the "begin" to instantiate (connect) the clock buffer, and wire it to the right pins.
 
 
 
Austin Lesea
Principal Engineer
Xilinx San JoseView solution in original post

C，
在ucf文件中：
NET“clock_p”DIFF_TERM = TRUE; NET“clock_p”LOC = H14; NET“clock_n”DIFF_TERM = TRUE; NET“clock_n”LOC = H15;
然后在VHDL中，
port（clock_p，clock_n：在std_logic中;（等等，等等）
（声明接口......）
接着，
IBUFGDS_clock：IBUFGDS端口映射（O =>时钟， - 时钟缓冲输出I => clock_p， -  Diff_p时钟缓冲输入（连接到顶级端口）IB => clock_n  -  Diff_n时钟缓冲输入（直接连接到顶部）
-level port））;
在“开始”之后实例化（连接）时钟缓冲器，并将其连接到右侧引脚。
Austin Lesea主要工程师Xilinx San Jose



以下为原文

c,
 
In the ucf file:
 
NET "clock_p" DIFF_TERM = TRUE;
NET "clock_p" LOC=H14;
NET "clock_n" DIFF_TERM = TRUE;
NET "clock_n" LOC=H15;
 
And then in the VHDL,
 
port (          clock_p,clock_n : in std_logic;  (etc, etc, etc)


 (to declare the interfaces...)
 
and then,
 
IBUFGDS_clock : IBUFGDS
      port map (
     O => clock,  -- Clock buffer output
     I => clock_p,  -- Diff_p clock buffer input (connect to top-level port)
    IB => clock_n -- Diff_n clock buffer input (connect directly to top-level port)
      );


after the "begin" to instantiate (connect) the clock buffer, and wire it to the right pins.
 
 
 
Austin Lesea
Principal Engineer
Xilinx San Jose

谢谢，这很有效。



以下为原文

Thanks, that worked.

对不起，我认为它有效，因为它帮助我克服了以前的错误。
但现在我在Map过程中遇到了新的错误：
错误：Pack：1107  -  Pack无法将下面列出的符号组合到单个IOB组件中，因为所选的站点类型不兼容。
进一步说明：组件已有输入从属缓冲区。
涉及的符号：PAD符号“clkn”（填充信号= clkn）SlaveBuffer符号“IBUFGDS_clock / SLAVEBUF.DIFFIN”（输出信号= IBUFGDS_clock / SLAVEBUF.DIFFIN）SlaveBuffer符号“proc / ibufgds_0 / SLAVEBUF.DIFFIN”（输出信号= proc /
ibufgds_0 / SLAVEBUF.DIFFIN）错误：Pack：1107  -  Pack无法将下面列出的符号组合到单个IOB组件中，因为所选的站点类型不兼容。
进一步说明：I / O组件已拥有输入缓冲区。
涉及的符号：PAD符号“clkp”（填充信号= clkp）DIFFAMP符号“IBUFGDS_clock / IBUFDS”（输出信号= clk）DIFFAMP符号“proc / ibufgds_0 / IBUFDS”（输出信号= proc / dcm_clk_s）
我使用约束来试图强制合成器不要将自己的缓冲区放在clkp和clkn上，但它似乎忽略了它们，或者其他东西。
。
。
我不知道如何解决这个问题。
这些是我使用的约束：
attribute buffer_type：string; clkp的属性buffer_type：signal是“none”; clkn的属性buffer_type：signal是“none”;



以下为原文

Sorry, I THOUGHT it was working, because it helped me get past the errors that I was previously having.  But now I have new errors during the Map process:
 
ERROR:Pack:1107 - Pack was unable to combine the symbols listed below into a
   single IOB component because the site type selected is not compatible.

   Further explanation:
   The component already has an input slave buffer.
   Symbols involved:
       PAD symbol "clkn" (Pad Signal = clkn)
       SlaveBuffer symbol "IBUFGDS_clock/SLAVEBUF.DIFFIN" (Output Signal =
   IBUFGDS_clock/SLAVEBUF.DIFFIN)
       SlaveBuffer symbol "proc/ibufgds_0/SLAVEBUF.DIFFIN" (Output Signal =
   proc/ibufgds_0/SLAVEBUF.DIFFIN)

ERROR:Pack:1107 - Pack was unable to combine the symbols listed below into a
   single IOB component because the site type selected is not compatible.

   Further explanation:
   The I/O component already owns an input buffer.
   Symbols involved:
       PAD symbol "clkp" (Pad Signal = clkp)
       DIFFAMP symbol "IBUFGDS_clock/IBUFDS" (Output Signal = clk)
       DIFFAMP symbol "proc/ibufgds_0/IBUFDS" (Output Signal = proc/dcm_clk_s)


I used constraints to attempt to force the synthesizer not to put its own buffers on clkp and clkn, but it seems to be ignoring them, or something . . . I don't know how to solve this.  These are the constraints I used:
 
attribute buffer_type: string;
attribute buffer_type of clkp: signal is "none";
attribute buffer_type of clkn: signal is "none";

C，
我从未使用你发布的约束...
如果你把他们留下怎么办？
Austin Lesea主要工程师Xilinx San Jose



以下为原文

c,
 
I have never used the constraints you posted...

What happens if you leave them out?
 
 
Austin Lesea
Principal Engineer
Xilinx San Jose

我试图省略约束，因此我必须关闭合成器的-iobuf属性，所以我手动将IBUF和OBUF添加到我的所有引脚。
在Map中我仍然有相同的“Pack无法组合符号”错误。



以下为原文

I tried leaving out the constraints, which necessitated that I turn off the synthesizer's -iobuf property, so I manually added IBUFs and OBUFs to all my pins.  I still got the same "Pack was unable to combine the symbols" errors during Map.

我只是指你在上一封电子邮件中列出的三个属性缓冲区类型约束，
正如我所讨论的三条线路正在干扰差异化IBUFG的位置。
IBUF和OBUF用于IO引脚，需要任何约束来告诉工具如何处理IO引脚。
差分IBUFG用于（输入时钟网络，并且是为了将（差分）时钟引入器件所必需的。
Austin Lesea主要工程师Xilinx San Jose



以下为原文

I was referring to only the three attribute buffer type constraints you listed in a previous email,

As those are the three lines which I blieve are interfering with the placement of the differentiual IBUFG.
 
IBUF and OBUF are for IO pins, and any constraints for those are needed to tell the tools what to do with the IO pins.
 
The differential IBUFG is for the (input_ clock network, and is required in order to get a (differential) clock into the device.
 
 
 
Austin Lesea
Principal Engineer
Xilinx San Jose

“我只是指你在前一封电子邮件中列出的三个属性缓冲区类型限制，”
是的，我把它们排除在外并得到同样的错误。
我只提到了其他的东西，以便你知道更广泛的背景（即我现在关闭了iobuf自动放置）。



以下为原文

"I was referring to only the three attribute buffer type constraints you listed in a previous email,"
 
Right, I left those out and got the same error.  I only mentioned the other things so that you'd know the broader context (i.e. I now have the iobuf auto-placement turned off).

我终于能够解决问题了。
似乎问题是尝试使用相同的时钟信号驱动两个不同的时钟缓冲器。
我进入了XPS为我的处理器生成的VHDL代码，并对其进行了修改，以便从处理器的缓冲区出来的时钟将从我的处理器端口出来，并可用于我的其他组件。
然后我摆脱了我在顶层代码中添加的额外IBUFG。
现在一切似乎都没问题。



以下为原文

I was finally able to fix the problem.  It seems the issue was trying to have the same clock signals driving two different clock buffers.  I got into the VHDL code that XPS had generated for my processor, and modified it so that the clock coming out of the processor's buffer would come out my processor's port and be available for my other components.  Then I got rid of the extra IBUFG that I had put in my top-level code.  Everything seems to be okay now.

我在使用ML605板上的差分引脚（V6  -  LX240T  -  1156）驱动MGTREFCLK时遇到了类似的问题。
如果要使用SMA引脚，差分缓冲器是根据ML605 UG通过引脚F5和F6（n和p）驱动的IBUFGDS。
IBUFGDS在我的HDL中。
但是，F5和F6驱动IBUFDS（与IBUFGDS相同？）因此，提前计划将时钟io推出到AD 25和26，后者驱动到FMC P和N对。
我尝试使用这篇文章中给出的约束，但是planahead不接受它（我分配给F5和F6而不是H14和15）。



以下为原文

I am having a similar issue with driving the MGTREFCLK using the differential pins on the ML605 board (V6 - LX240T - 1156).
 
The differential buffer is IBUFGDS driven through pins F5 and F6 (n and p) according to the ML605 UG if you want to use the SMA pins. IBUFGDS is in my HDL.
 
However, F5 and F6 drive an IBUFDS (same as IBUFGDS?) so plan ahead keeps pushing the clock io out to AD 25 and 26 which drive to an FMC P and N pair.
 
I tried using the constraint given in this post, but planahead won't accept it (I assign to F5 and F6 instead of H14 and 15).
 
 

MGT参考时钟输入需要为Virtex-6器件使用IBUFDS_GTXE1原语。
------您是否尝试在Google中输入问题？
如果没有，你应该在发布之前。太多结果？
尝试添加网站：www.xilinx.com



以下为原文

The MGT reference clock inputs need to use the IBUFDS_GTXE1 primitive for Virtex-6 devices.
------Have you tried typing your question into Google?  If not you should before posting.
Too many results?  Try adding site:www.xilinx.com

这给出了以下错误：
错误：HDLCompiler：432  - “ Xilinx  sum_lock  sum_lock_top.vhd”第146行：正式没有实际值或默认值。
仅使用IBUFDS不会产生合成错误，但它也会返回IBUFGDS引脚，并且不允许我移动引脚。
IBUFDS_GTXE1上有任何文件吗？
GTX UG说要使用IBUFDS，但它所指的时钟资源指南没有提到它，我在语言模板中找不到IBUFDS。



以下为原文

 
That gives the following error:ERROR:HDLCompiler:432 - "Xilinxsum_locksum_lock_top.vhd" Line 146: Formal has no actual or default value.Just using an IBUFDS does not give a synthesis error, but it also routes back to the IBUFGDS pin and won't allow me to move the pin.Is there any documentation on the IBUFDS_GTXE1? The GTX UG says to use an IBUFDS, but the clocking resources guide it refers to doesn't mention it and I couldn't find IBUFDS in the language template. 

>错误：HDLCompiler：432  - “ Xilinx  sum_lock  sum_lock_top.vhd”第146行：正式没有实际值或默认值。
似乎与MGT参考时钟没有任何关系，并且必须与代码中的其他问题相关
> GTX UG表示要使用IBUFDS，
您在UG366中的哪个位置？
在我看到的任何地方都说要使用IBUFDS_GTXE1。
------您是否尝试在Google中输入问题？
如果没有，你应该在发布之前。太多结果？
尝试添加网站：www.xilinx.com



以下为原文

> ERROR:HDLCompiler:432 - "Xilinxsum_locksum_lock_top.vhd" Line 146: Formal has no actual or default value.
 
Appears to have no relationship to the MGT reference clock and must be related to some other issue in your code
 
> The GTX UG says to use an IBUFDS,
 
Where do you see this in UG366?  Everywhere that I see says IBUFDS_GTXE1 is to be used.
------Have you tried typing your question into Google?  If not you should before posting.
Too many results?  Try adding site:www.xilinx.com

UG366很好，它说IBUFDS_GTXE1。
IBUFDS不在时钟资源指南中，因此它很混乱，因为那里和语言模板中最接近的是IBUFGDS。



以下为原文

The UG366 is fine, it says IBUFDS_GTXE1. IBUFDS is not in the clocking resources guide so it is confusing because the closest thing there and in the language templates is the IBUFGDS.

...谢谢你的帮助。
引脚排列现在正常工作。



以下为原文

... and thanks for your help. The pinout works now.

我有类似的错误。
我试图在chipcope上看到差分时钟的输出。我正在使用Spartan 6 sp601板。
entity diff_clock是port（CLK_P：在std_logic中; CLK_N：在std_logic中; clkout：out std_logic）;
结束diff_clock;
架构diff_clock的行为是信号a：std_logic;
开始U_IBUFGDS：ibufgds通用映射（IOSTANDARD =>“LVDS_25”）端口映射（O => a，I => CLK_P，IB => CLK_N）;
过程（a）开始clkout结束过程;
结束行为;
错误：NgdBuild：924  - 输入焊盘网络'CLK_P'正在驱动非缓冲基元：
请帮帮我



以下为原文

I am having the similar error. I am trying to see the output of differential clock on chipscope.I am using Spartan 6 sp601 board.
 
entity diff_clock is
 port
  (
    CLK_P       : in  std_logic;
     CLK_N       : in  std_logic;
    clkout     : out std_logic
  );
end diff_clock;
 
architecture Behavioral of diff_clock is
signal a : std_logic;
begin
U_IBUFGDS : ibufgds
   generic map  
   (
     IOSTANDARD => "LVDS_25"
    )
   port map  
    (    
     O => a,  
     I => CLK_P,
      IB => CLK_N
    );
process(a)
begin
clkout <= a;
end process;
end Behavioral;
 
 
ERROR:NgdBuild:924 - input pad net 'CLK_P' is driving non-buffer primitives:
 
 
Please help me

aryankumar写道：
我有类似的错误。
我试图在chipcope上看到差分时钟的输出。我正在使用Spartan 6 sp601板。
那是因为您无法使用ChipScope查看时钟信号。
ChipScope只能查看非时钟（非全局）网络上的信号，当然时钟将在全球网络上。
因此，错误。
----------------------------是的，我这样做是为了谋生。



以下为原文

aryankumar wrote:
I am having the similar error. I am trying to see the output of differential clock on chipscope.I am using Spartan 6 sp601 board.

That's because you can't use ChipScope to look at a clock signal. ChipScope can only look at signals on non-clock (non-global) nets, and of course a clock will be on a global net. Hence, the error.
----------------------------Yes, I do this for a living.