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嗨,
当我尝试从Spartan-6 CSG484LX150输出数据时出现以下错误: 错误:位置:1318 - 用户具有过度约束的组件serializeData_oser_driver。 没有可放置的站点满足用户约束。 请查看驱动程序组件的用户约束以及serializeData_oser_driver的加载组件。 serializeData_oser_driver是一个驱动6个OSERDES的BUFPLL。 每个OSERDES驱动一个名为oData的std_logic_vector元素,它是输出向量。 我验证了“Spartan-6 FPGA封装和引脚产品规格UG385(v2.2)2011年8月24日”,以确保连接到oData的所有引脚都属于同一个IOBank(编号2)。 ucf文件位于此消息的末尾。 我不知道什么是错的。 net“rsTx”loc = C6 | iostandard = LVCMOS33; net“rsRx”loc = D6 | iostandard = LVCMOS33; net“clk”loc = AA12; net“oClk”loc = AB10 | iostandard = LVCMOS33; net“oData(5)”loc = Y6 | iostandard = LVCMOS33; net“oData(4)”loc = W9 | iostandard = LVCMOS33; net“oData(3)”loc = AB9 | iostandard = LVCMOS33; net“oData(2)”loc = W6 | iostandard = LVCMOS33; net“oData(1)”loc = Y8 | iostandard = LVCMOS33; net“oData(0)”loc = Y9 | iostandard = LVCMOS33; net“transceiverShutdownA”loc = AB13 | iostandard = LVCMOS33; net“rxPwrDwnA”loc = AB15 | iostandard = LVCMOS33; net“txPwrDwnA”loc = AB14 | iostandard = LVCMOS33; net“resetA”loc = Y4 | iostandard = LVCMOS33; net“transceiverShutdownB”loc = A11 | iostandard = LVCMOS33; net“rxPwrDwnB”loc = B6 | iostandard = LVCMOS33; net“txPwrDwnB”loc = A6 | iostandard = LVCMOS33; net“resetB”loc = M7 | IOSTANDARD = LVCMOS33; 先谢谢你, JoãoAlmeida 以上来自于谷歌翻译 以下为原文 Hi, I'm having the following error when I try to output data from a Spartan-6 CSG484LX150: ERROR:Place:1318 - User has over-constrained component serializeData_oser_driver. There are no placeable sites that satisfy the user constraints. Please review the user constraints on the driver component and the load components of serializeData_oser_driver. serializeData_oser_driver is a BUFPLL that is driving 6 OSERDES. Each OSERDES drives a element of a std_logic_vector named oData, which is the output vector. I verified "Spartan-6 FPGA Packaging and Pinouts Product Specification UG385 (v2.2) August 24, 2011" to be sure that all pins connected to oData belong to the same IOBank (number 2). The ucf file is at the end of this message. I don't know what could be wrong. net "rsTx" loc=C6 | iostandard=LVCMOS33; net "rsRx" loc=D6 | iostandard=LVCMOS33; net "clk" loc=AA12; net "oClk" loc=AB10 | iostandard=LVCMOS33; net "oData(5)" loc=Y6 | iostandard=LVCMOS33; net "oData(4)" loc=W9 | iostandard=LVCMOS33; net "oData(3)" loc=AB9 | iostandard=LVCMOS33; net "oData(2)" loc=W6 | iostandard=LVCMOS33; net "oData(1)" loc=Y8 | iostandard=LVCMOS33; net "oData(0)" loc=Y9 | iostandard=LVCMOS33; net "transceiverShutdownA" loc=AB13 | iostandard=LVCMOS33; net "rxPwrDwnA" loc=AB15 | iostandard=LVCMOS33; net "txPwrDwnA" loc=AB14 | iostandard=LVCMOS33; net "resetA" loc=Y4 | iostandard=LVCMOS33; net "transceiverShutdownB" loc=A11 | iostandard=LVCMOS33; net "rxPwrDwnB" loc=B6 | iostandard=LVCMOS33; net "txPwrDwnB" loc=A6 | iostandard=LVCMOS33; net "resetB" loc=M7 | iostandard=LVCMOS33; Thank you in advance, João Almeida |
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嗨,
删除/注释ucf中组件“serializeData_oser_driver”的源和负载的约束,并查看它是否通过了实现过程。 谢谢。 -------------------------------------------------- ------------------------------------------您是否尝试在Google中输入问题? ? 如果没有,你应该在发布之前。 此外,MARK这是一个答案,以防它有助于解决您的查询/问题。给予帮助您找到解决方案的帖子。 以上来自于谷歌翻译 以下为原文 Hi, Remove/comment the constraints on the sources and loads of the component "serializeData_oser_driver" in the ucf and see whether it passes the implementation process. Thanks. -------------------------------------------------------------------------------------------- Have you tried typing your question in Google? If not you should before posting. Also, MARK this is as an answer in case it helped resolve your query/issue.Give kudos to the post that helped you to find the solution. |
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嗨,
另外,对于BUFPLL,有以下声明 使用PLL时钟输出时,PLL的CLKOUT0或CLKOUT1必须直接连接到PLLIN时钟输入。 确保您遵循此。 同时在PlanAhead中打开IMPLEMENTED设计,并检查由BUFPLL驱动的所有OSERDES组件锁定到同一个BANK的位置。 谢谢,AnirudhPS:请将此标记作为答案,以防它有助于解决您的问题。如果帖子引导您找到解决方案,请给予赞誉。 以上来自于谷歌翻译 以下为原文 Hi, In addition UG382 has the following statement with regards to BUFPLL's When using the PLL clock outputs, CLKOUT0 or CLKOUT1 from the PLL must directly connect to the PLLIN clock input. Make sure you are following this. Also open IMPLEMENTED design in PlanAhead and check where all the OSERDES components driven by the BUFPLL are locked to the same BANK. Thanks, Anirudh PS: Please MARK this as an answer in case it helped resolve your query.Give kudos in case the post guided you to a solution. |
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谢谢,但错误仍然存在。
但是我改变了输出引脚的位置,错误消失了。 我想知道为什么。 新的ucf如下所示。 #net“rsTx”loc = C6 | iostandard = LVCMOS33; #net“rsRx”loc = D6 | iostandard = LVCMOS33; #net“clk”loc = AA12; #net“oClk”loc = T2 | iostandard = LVCMOS33; #net“oData(5)”loc = G4 | iostandard = LVCMOS33; #net“oData(4)”loc = E5 | iostandard = LVCMOS33; #net“oData(3)”loc = F7 | iostandard = LVCMOS33; #net“oData(2)”loc = D5 | iostandard = LVCMOS33; #net“oData(1)”loc = F5 | iostandard = LVCMOS33; #net“oData(0)”loc = E6 | iostandard = LVCMOS33; ## net“transceiverShutdownA”loc = AB13 | iostandard = LVCMOS33; #net“rxPwrDwnA”loc = AB15 | iostandard = LVCMOS33; #net“txPwrDwnA”loc = AB14 | iostandard = LVCMOS33; #net“resetA”loc = Y4 | iostandard = LVCMOS33; #net“transceiverShutdownB”loc = A11 | iostandard = LVCMOS33; #net“rxPwrDwnB”loc = B6 | iostandard = LVCMOS33; #net“txPwrDwnB”loc = A6 | iostandard = LVCMOS33; #net“resetB”loc = M7 | IOSTANDARD = LVCMOS33; 以上来自于谷歌翻译 以下为原文 Thank you, but the error persists. However I changed the location of output pins and the error disappeared. I would like to know why. The new ucf is listed below. #net "rsTx" loc=C6 | iostandard=LVCMOS33; #net "rsRx" loc=D6 | iostandard=LVCMOS33; #net "clk" loc=AA12; #net "oClk" loc=T2 | iostandard=LVCMOS33; #net "oData(5)" loc=G4 | iostandard=LVCMOS33; #net "oData(4)" loc=E5 | iostandard=LVCMOS33; #net "oData(3)" loc=F7 | iostandard=LVCMOS33; #net "oData(2)" loc=D5 | iostandard=LVCMOS33; #net "oData(1)" loc=F5 | iostandard=LVCMOS33; #net "oData(0)" loc=E6 | iostandard=LVCMOS33; # #net "transceiverShutdownA" loc=AB13 | iostandard=LVCMOS33; #net "rxPwrDwnA" loc=AB15 | iostandard=LVCMOS33; #net "txPwrDwnA" loc=AB14 | iostandard=LVCMOS33; #net "resetA" loc=Y4 | iostandard=LVCMOS33; #net "transceiverShutdownB" loc=A11 | iostandard=LVCMOS33; #net "rxPwrDwnB" loc=B6 | iostandard=LVCMOS33; #net "txPwrDwnB" loc=A6 | iostandard=LVCMOS33; #net "resetB" loc=M7 | iostandard=LVCMOS33; |
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嗨athandr,
我正在使用clk_out1直接连接到BUFPLL的PLLIN时钟输入。 我不理解你提出的第二个建议。 每个IO引脚都属于FPGA中的特定BANK,好的。 但是每个OSERDES组件也有相关的BANK吗? 谢谢, JoãoAlmeida 以上来自于谷歌翻译 以下为原文 Hi athandr, I'm using clk_out1 directly connected to the PLLIN clock input of BUFPLL. I'm not understanding the second suggestion you gave. Each IO pin belong to a specific BANK in FPGA, ok. But each OSERDES component, have a associated BANK, too? Thank you, João Almeida |
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嗨,
我的意思是检查OSERDES组件是否锁定到IO库所在的同一时钟区域。 但是我想他们应该被锁定在同一个地区。 你可以交叉检查吗? 但是,打开IMPLEMENTED设计并右键单击BUFPLL并选择“Show Connectivity”。 这应该显示从BUFPLL到OSERDES的所有连接,再次在OSERDES上右键单击并选择“Show Connectivity”以查看从BUFPLL到IO的整个连接。 这应该显示任何非法连接或所有连接都已正确制作。 谢谢,AnirudhPS:请将此标记作为答案,以防它有助于解决您的问题。如果帖子引导您找到解决方案,请给予赞誉。 以上来自于谷歌翻译 以下为原文 Hi, What i meant was to check if the OSERDES components were locked to the same Clock Region where the IO bank exists. However i guess they should be locked to the same region. Can you crosscheck that. However open the IMPLEMENTED design and right click on the BUFPLL and select "Show Connectivity". This should show all the connections from the BUFPLL to the OSERDES and on the OSERDES again right click and select "Show Connectivity" to see the entire connectivity from the BUFPLL to the IO's. This should show any illegal connections or if all the connectiions have been properly made. Thanks, Anirudh PS: Please MARK this as an answer in case it helped resolve your query.Give kudos in case the post guided you to a solution. |
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