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我正在尝试在kintex-7 FPGA中构建一个运行速度为5Gbps的JESD204B ADC和DAC接口。 根据产品指南文档,我在vivado 2014.1中生成了发送和接收内核,更新了“支持”块以支持双向数据流(共享收发器逻辑),更新了收发器线路速率,替换了* _gtwizard_gt_0文件,然后合成 “支持”模块生成接口dcp。 当我使用生成的dcp构建逻辑时,它的计时失败。 故障可以追溯到dcp,结果发现tx_core_clk和rx_core_clk被限制在6.4ns(156.25MHz),就像原来的JESD204内核一样。 在我的设计中,这些时钟是250MHz,并且在顶级xdc文件中被限制为4ns。 似乎顶级约束不会覆盖dcp的约束。 如何覆盖TX / RX JESD204 dcps中嵌入的约束以匹配提供的tx / rx内核时钟? 问候, Shant 以上来自于谷歌翻译 以下为原文 Hi all, I'm trying to build a JESD204B ADC and DAC interface that runs at 5Gbps in a kintex-7 FPGA. Following the product guide document, I generated the transmit and receive cores in vivado 2014.1, updated the "support" block to support data flow in both directions (shared transceiver logic), updated the transceivers line rate, replaced the *_gtwizard_gt_0 file, then synthesized the "support" module to generate the interface dcp. When I built the logic with the generated dcp, it failed timing. The failure was traced back to the dcp where it turned out the tx_core_clk and rx_core_clk were constrained to 6.4ns (156.25MHz) just like in the original JESD204 core. In my design, these clocks are 250MHz and are constrained to 4ns in a top level xdc file. It seems like the top level constraints are not overriding the dcp's constraints. How can I override the constraints embedded in the TX/RX JESD204 dcps to match the supplied tx/rx core clocks? Regards, Shant |
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嗨,
JESD IP的时钟约束在_ooc.xdc中定义。 此XDC文件将仅在脱离上下文流程中读取。 以下是此文件中的相同行。 #此约束文件包含在上下文流程中使用的默认时钟频率,例如#OOC Synthesis和Hierarchical Designs。 为获得最佳效果,应修改频率#以匹配目标频率。 #此约束文件未在正常的自上而下合成中使用(Vivado的默认流程) 因此,此约束文件不会用于顶级综合或实现。 这些约束仅用于指导OOC运行。 在您的情况下,我看到您在顶级模块的综合属性中设置了-mode out_of_context。 这实际上是在脱离上下文模式下运行顶级综合。 在此流程中,该工具也在顶级综合中读取IP的_ooc.xdc。 当我在顶级综合设置中删除-mode out_of_context并且在顶级XDCjesd204_8tx_4rx_support_tim.xdc文件中只有以下约束时,我发现内核中的同步元素也受限于此顶级XDC中提到的值。 create_clock -period 4.0 -name gbtclk [get_ports refclk_p] #将Tx和Rx设备时钟设置为250MHzcreate_clock -period 4.0 -name txclk [get_ports txclk_p] create_clock -period 4.0 -name rxclk [get_ports rxclk_p] 如果要在OOC模式下运行顶级综合,则可以禁用IP XDC文件_ooc.xdc并在顶层定义这些时钟。 谢谢, 迪皮卡。 谢谢,迪皮卡.---------------------------------------------- ---------------------------------------------- Google之前的问题 张贴。 如果某人的帖子回答了您的问题,请将帖子标记为“接受为解决方案”。 如果你看到一个特别好的和信息丰富的帖子,考虑给它Kudos(左边的明星) 在原帖中查看解决方案 以上来自于谷歌翻译 以下为原文 Hi, The clock constraint of JESD IP are defined in _ooc.xdc. This XDC file will be read in out of context flow alone. Below are the lines from this file which say the same. # This constraints file contains default clock frequencies to be used during out-of-context flows such as # OOC Synthesis and Hierarchical Designs. For best results the frequencies should be modified # to match the target frequencies. # This constraints file is not used in normal top-down synthesis (the default flow of Vivado) So this constraint file will not be used in top level synthesis or implementation. These constraints are only used to direct OOC run. In your case I see that you had set -mode out_of_context in synthesis properties for top level module. This actually runs top level synthesis in out of context mode. During this flow the tool is reading the _ooc.xdc of IP in the top level synthesis too. When I removed -mode out_of_context in top level synthesis settings and had only the below constraints in top XDC jesd204_8tx_4rx_support_tim.xdc file, I see that the sync elements inside the cores are also constrained to the values mentioned in this top XDC. create_clock -period 4.0 -name gbtclk [get_ports refclk_p] # Set Tx and Rx Device Clocks to 250MHz create_clock -period 4.0 -name txclk [get_ports txclk_p] create_clock -period 4.0 -name rxclk [get_ports rxclk_p] If you want to run top level synthesis in OOC mode then you can disable the IP XDC file _ooc.xdc and define these clocks at top level. Thanks, Deepika. Thanks, Deepika. -------------------------------------------------------------------------------------------- Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left)View solution in original post |
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嗨Shant,
您可以更改XDC文件的处理顺序,以使顶级约束覆盖IP约束。 查看这篇文章http://www.xilinx.com/support/answers/52947.html 检查这是否有帮助。 谢谢, 迪皮卡。 谢谢,迪皮卡.---------------------------------------------- ---------------------------------------------- Google之前的问题 张贴。 如果某人的帖子回答了您的问题,请将帖子标记为“接受为解决方案”。 如果你看到一个特别好的和信息丰富的帖子,考虑给它Kudos(左边的明星) 以上来自于谷歌翻译 以下为原文 Hi Shant, You can change the processing order of XDC files to make top level constraint overwrite IP constraints. Check this article http://www.xilinx.com/support/answers/52947.html Check if this helps. Thanks, Deepika. Thanks, Deepika. -------------------------------------------------------------------------------------------- Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left) |
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嗨Deepika,
感谢您的快速回复。 我添加了一个带有时序覆盖约束的xdc(create_clock -period 4 [get_pins inst_jesd204_8l_tx / tx_core_clk]),将其PROCESSING_ORDER设置为LATE,然后重建dcp.dcp内置约束覆盖工作并且如时钟网络报告中所报告的那样tx_core_clk 在inst_jesd204_8l_tx内核实例中设置为250MHz而不是默认的156.25MHz。 问题是更新的时序约束仅适用于inst_jesd204_8l_tx级别的逻辑(即约束仅向下传播)。 在顶层逻辑级别,在“support”模块中,tx_core_clk也用于为i_gtwizard_top模块提供时钟。 由时钟计时的路径在时钟网络报告中显示为不受约束。 约束顶级时钟(create_clock -period 4 -name tx_core_clk_bufg [get_pins i_shared_clocks / inst_bufg_txclk / O]),然后重建dcp并检查时钟报告,使该工具认为有两个不同的时钟,tx_core_clk和inst_jesd204_8l_tx / tx_core_clk。 这两个域之间的路径交叉失败。 任何建议如何进行? 提前致谢, Shant 以上来自于谷歌翻译 以下为原文 Hi Deepika, Thanks for the prompt reply. I added an xdc with the timing override constraints (create_clock -period 4 [get_pins inst_jesd204_8l_tx/tx_core_clk]), set its PROCESSING_ORDER to LATE, then rebuilt the dcp. The dcp built-in constraints overriding worked and as reported in the clock network report the tx_core_clk within the inst_jesd204_8l_tx core instance was set to 250MHz as opposed to the default 156.25MHz. The problem is the updated timing constraint applies only to logic at the inst_jesd204_8l_tx level (i.e the constraints propagate downwards only). At the top logic level, in the "support" module, the tx_core_clk is also used to clock the i_gtwizard_top module. Paths clocked by this clock showed up as unconstrained in the clock network report. Constraining the top level clock (create_clock -period 4 -name tx_core_clk_bufg [get_pins i_shared_clocks/inst_bufg_txclk/O]) and then rebuilding the dcp and checking the clock report, makes the tool think there are two different clocks, tx_core_clk and inst_jesd204_8l_tx/tx_core_clk. Paths crossing between these two domains fail timing. Any recommendation how to proceed? Thanks in advance, Shant |
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嗨Shant,您可以尝试在主端口(顶级端口)上进行时钟处理吗?
不要在bufg输出或jesd核心输入上定义时钟。检查工具是否能够传播这个顶级时钟。同样当你从引脚指定时钟约束时,在你的情况下说bufg输出,工具将不会考虑bufg之前的路径延迟 计算,因此建议在主端口上定义时钟。如果要重命名或覆盖工具,请在mmcm输出上自动生成约束,使用create_generated_clock约束。谢谢,Deepika。 谢谢,迪皮卡.---------------------------------------------- ---------------------------------------------- Google之前的问题 张贴。 如果某人的帖子回答了您的问题,请将帖子标记为“接受为解决方案”。 如果你看到一个特别好的和信息丰富的帖子,考虑给它Kudos(左边的明星) 以上来自于谷歌翻译 以下为原文 Hi Shant, Can you try deifing the clock on the primary port(top level port)? Donot define the clock on bufg output or jesd core input. Check if the tool is able to propagate this top level clock. Also when you specify clock constraint from pins say bufg output in your case the tool will not consider the path before bufg in delay calculation, hence it is recommended to define the clocks on primary ports. In case if you want to rename or override the tool auto generated constraints on mmcm outputs use create_generated_clock constraint. Thanks, Deepika.Thanks, Deepika. -------------------------------------------------------------------------------------------- Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left) |
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嗨Deepika,
我确实尝试将顶级端口时钟(在BUFG之前)限制在250MHz,但问题是该工具仍然认为JESD IP内部的tx_core_clk是156.25MHz,因此失败了时序。 然后我试着约束BUFG输出并得到同样的失败。 只能通过将IP内部的相同时钟约束到所需速率来覆盖JESD IP时钟。 有没有办法只删除JESD IP约束而不是覆盖它? 当IP中没有约束时钟时,可能会限制顶层时钟传播到IP? 谢谢, Shant 以上来自于谷歌翻译 以下为原文 Hi Deepika, I did try constraining the top level port clock (before the BUFG) to 250MHz, but the problem was the tool was still thinking the tx_core_clk inside the JESD IP was 156.25MHz and thus failing timing. Then I tried constraining the BUFG output and got the same failure. The JESD IP clock can only be overridden by constraining the same clock inside the IP to the desired rate. Is there a way to just remove the JESD IP constraint instead of overriding it? Maybe constraining the top level clock propagates to the IP when there is no constrained clock in the IP? Thanks, Shant |
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嗨Deepika,
由于更新的时序约束更严格,因此生成JESD204 IP的加密RTL文件并使用具有修改时序约束的文件来构建“支持”级别的脱离上下文dcp是不合理的,然后将其包含在顶部 级逻辑构建? 这样,合成结果可能更适合于更严格的约束时钟,而不是仅仅覆盖已经合成的dcp中的原始约束? 问候, Shant 以上来自于谷歌翻译 以下为原文 Hi Deepika, Since the updated timing constraints are tighter, doesn't it make sense to generate the JESD204 IP's encrypted RTL files and use those files with modified timing constraints to build the out of context dcp for the "support" level which is then included in the top level logic build? This way the synthesis results might be more suitable for the tighter constrained clocks instead of just overriding the original constrained in an already synthesized dcp? Regards, Shant |
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嗨Shant,
你能附上一张显示你设计时钟的快照吗? 是否有可能分享设计? 通过取消选中IP XDC文件的“IS_ENABLED”属性,可以对IP XDC文件进行分配。 但为此你需要在设计中使用IP XCI文件(而不是DCP)。 谢谢, 迪皮卡。 谢谢,迪皮卡.---------------------------------------------- ---------------------------------------------- Google之前的问题 张贴。 如果某人的帖子回答了您的问题,请将帖子标记为“接受为解决方案”。 如果你看到一个特别好的和信息丰富的帖子,考虑给它Kudos(左边的明星) 以上来自于谷歌翻译 以下为原文 Hi Shant, Can you attach a snapshot showing the clocking in your design? Is it possible to share the design? It is possible to dia***le the IP XDC files by unchecking "IS_ENABLED" property of the IP XDC file. But for this you need to use IP XCI file in the design (not the DCP). Thanks, Deepika. Thanks, Deepika. -------------------------------------------------------------------------------------------- Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left) |
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无法编辑或删除IP约束。
要修改与IP一起提供的约束,您必须: (1)禁用相应的IP XDC文件; (2)将约束复制到您的XDC文件; (3)根据需要编辑约束。 但在这种情况下,在OOC IP运行期间不会读取您的XDC文件。 但是,在实施过程中,将考虑修改的约束。 谢谢, 迪皮卡。 谢谢,迪皮卡.---------------------------------------------- ---------------------------------------------- Google之前的问题 张贴。 如果某人的帖子回答了您的问题,请将帖子标记为“接受为解决方案”。 如果你看到一个特别好的和信息丰富的帖子,考虑给它Kudos(左边的明星) 以上来自于谷歌翻译 以下为原文 IP constraints cannot be edited or deleted. In order to modify a constraint delivered withan IP, you must: (1) disable the corresponding IP XDC file; (2) copy the constraint to your XDC file; and (3) edit the constraint as desired. But in this case, your XDC file will not be read during OOC IP run. However during implementation the modified constraints will be taken in to account. Thanks, Deepika. Thanks, Deepika. -------------------------------------------------------------------------------------------- Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left) |
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嗨Deepika,
除了IP生成和脱离上下文的dcp编译脚本之外,还附带了自定义源和xdc文件。 完成dcp合成,运行report_timing_summary命令并检查时序故障后,您可以看到该工具如何将“支持”级别的JESD IP输入时钟视为与内部时钟不同的时钟。 提前致谢, Shant jesd_support.zip 17 KB 以上来自于谷歌翻译 以下为原文 Hi Deepika, Attached are the customized source and xdc files in addition to the IPs generation and out of context dcp compilation script. After finishing the dcp synthesis, running the report_timing_summary command and examining the timing failures, you can see how the tool is treating the JESD IPs input clock at the "support" level as a different clock from the internal clock. Thanks in advance, Shant |
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嗨,
JESD IP的时钟约束在_ooc.xdc中定义。 此XDC文件将仅在脱离上下文流程中读取。 以下是此文件中的相同行。 #此约束文件包含在上下文流程中使用的默认时钟频率,例如#OOC Synthesis和Hierarchical Designs。 为获得最佳效果,应修改频率#以匹配目标频率。 #此约束文件未在正常的自上而下合成中使用(Vivado的默认流程) 因此,此约束文件不会用于顶级综合或实现。 这些约束仅用于指导OOC运行。 在您的情况下,我看到您在顶级模块的综合属性中设置了-mode out_of_context。 这实际上是在脱离上下文模式下运行顶级综合。 在此流程中,该工具也在顶级综合中读取IP的_ooc.xdc。 当我在顶级综合设置中删除-mode out_of_context并且在顶级XDCjesd204_8tx_4rx_support_tim.xdc文件中只有以下约束时,我发现内核中的同步元素也受限于此顶级XDC中提到的值。 create_clock -period 4.0 -name gbtclk [get_ports refclk_p] #将Tx和Rx设备时钟设置为250MHzcreate_clock -period 4.0 -name txclk [get_ports txclk_p] create_clock -period 4.0 -name rxclk [get_ports rxclk_p] 如果要在OOC模式下运行顶级综合,则可以禁用IP XDC文件_ooc.xdc并在顶层定义这些时钟。 谢谢, 迪皮卡。 谢谢,迪皮卡.---------------------------------------------- ---------------------------------------------- Google之前的问题 张贴。 如果某人的帖子回答了您的问题,请将帖子标记为“接受为解决方案”。 如果你看到一个特别好的和信息丰富的帖子,考虑给它Kudos(左边的明星) 以上来自于谷歌翻译 以下为原文 Hi, The clock constraint of JESD IP are defined in _ooc.xdc. This XDC file will be read in out of context flow alone. Below are the lines from this file which say the same. # This constraints file contains default clock frequencies to be used during out-of-context flows such as # OOC Synthesis and Hierarchical Designs. For best results the frequencies should be modified # to match the target frequencies. # This constraints file is not used in normal top-down synthesis (the default flow of Vivado) So this constraint file will not be used in top level synthesis or implementation. These constraints are only used to direct OOC run. In your case I see that you had set -mode out_of_context in synthesis properties for top level module. This actually runs top level synthesis in out of context mode. During this flow the tool is reading the _ooc.xdc of IP in the top level synthesis too. When I removed -mode out_of_context in top level synthesis settings and had only the below constraints in top XDC jesd204_8tx_4rx_support_tim.xdc file, I see that the sync elements inside the cores are also constrained to the values mentioned in this top XDC. create_clock -period 4.0 -name gbtclk [get_ports refclk_p] # Set Tx and Rx Device Clocks to 250MHz create_clock -period 4.0 -name txclk [get_ports txclk_p] create_clock -period 4.0 -name rxclk [get_ports rxclk_p] If you want to run top level synthesis in OOC mode then you can disable the IP XDC file _ooc.xdc and define these clocks at top level. Thanks, Deepika. Thanks, Deepika. -------------------------------------------------------------------------------------------- Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left) |
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