在SPC564A80B4上为bootloader工作没有系统时钟生成

您好，我配置为增强模式，用于系统时钟生成，我们的输入时钟为40Mhz外部晶振，需要产生150Mhz的系统时钟。由于不支持硬件检查CLKOUT引脚的系统时钟，因此我们配置了SCK时钟来计算系统时钟。
在ST提供的下面的代码中，我们在调试TRACE32中的代码时遇到了自由运行code（）的问题。
对于以下配置，代码运行一些异常情况。没有系统时钟生成。
FMPLL.ESYNCR2.R = 0x00000001;
FMPLL.ESYNCR1.R = 0xF005002D
而（FMPLL.SYNSR.B.LOCK！= 1）{}; / *等待FMPLL到LOCK * /
FMPLL.ESYNCR2.R = 0x00000000;
在ST提供的下面的代码中，我们在调试TRACE32中的代码时遇到了自由运行代码（调试端口失败）的问题。
对于以下配置，代码运行一些异常情况。没有系统时钟生成。

FMPLL.ESYNCR1.R = 0xF005002D;
而（FMPLL.SYNSR.B.LOCK！= 1）{}; / *等待FMPLL到LOCK * /
FMPLL.ESYNCR2.R = 0x00000000;在下面的代码中，我们参考了SPC564A80B4的参考手册。 。代码在调试条件下自由运行。
对于以下配置，系统时钟为72Mhz

FMPLL.ESYNCR1.R = 0xF005002D
而（FMPLL.SYNSR.B.LOCK！= 1）{}; / *等待FMPLL到LOCK * /
FMPLL.ESYNCR1.R | = 0x70000000;在下面的代码中，我们参考了SPC564A80B4的参考手册，但是在调试TRACE32中的代码时。
对于以下配置，系统时钟为150Mhz。

FMPLL.ESYNCR1.R = 0xF005002D
而（FMPLL.SYNSR.B.LOCK！= 1）{}; / *等待FMPLL到LOCK * /
FMPLL.ESYNCR1.R | = 0x70000000;请做好我们的解决方案解决这个问题，项目处于危急状态。如果有任何与问题相关的文件，请分享我下面提到的ID。
问候
Mahesh chamaraja
办公室ID：
邮寄地址：mahesh.chamaraja@kpit.com
电话***

## clock ## spc56 ## fmpll



以下为原文




Hello,  I configured in enhanced mode for system clock generation, our input clock is 40Mhz external crystal and need to generate 150Mhz  system clock. Since hardware is not supported to check CLKOUT pin for system clock, we configured SCK clock for calculating system clock.

• In below code used as provided by ST, but we facing a problem in free running the code () while debugging the code in TRACE32.
  For below configuration, code is running some exceptional condition. No system clock generation.
  FMPLL.ESYNCR2.R = 0x00000001;
  FMPLL.ESYNCR1.R = 0xF005002D
  while (FMPLL.SYNSR.B.LOCK != 1) {}; /* Wait for FMPLL to LOCK */
  FMPLL.ESYNCR2.R = 0x00000000;
  

• In below code used as provided by ST, but we facing a problem in free running the code ( debug port fail) while debugging the code in TRACE32.
  For below configuration, code is running some exceptional condition. No system clock generation.
     
  FMPLL.ESYNCR1.R = 0xF005002D;  
  while (FMPLL.SYNSR.B.LOCK != 1) {}; /* Wait for FMPLL to LOCK */  
  FMPLL.ESYNCR2.R = 0x00000000;
  

• In below code we referred reference manual of SPC564A80B4.  . The code is free running in debug condition.
  For below configuration, system clock is 72Mhz
  
  FMPLL.ESYNCR1.R = 0xF005002D
  while (FMPLL.SYNSR.B.LOCK != 1) {}; /* Wait for FMPLL to LOCK */
  FMPLL.ESYNCR1.R |= 0x70000000;
  

• In below code we referred reference manual of SPC564A80B4, but  while debugging the code in TRACE32.
  For below configuration, system clock is 150Mhz.
  
  FMPLL.ESYNCR1.R = 0xF005002D
  while (FMPLL.SYNSR.B.LOCK != 1) {}; /* Wait for FMPLL to LOCK */
  FMPLL.ESYNCR1.R |= 0x70000000;
  

Please do needful and give us solution resolve this issue, the project is in critical condition. If any documents related to issue please do share to my ID below mentioned.
Regards
Mahesh chamaraja
Office ID :
mailto:mahesh.chamaraja@kpit.com
Phone No : +917259205624

##clock ##spc56 ##fmpll