在斯巴达-6中路由资源饥饿？

m，看起来你用完了路径，所以它花了一个不太理想的。-verbose选项将列出所有路径及其时间。线路有多个地方被路由（重新使用），以便“大多数”设计
满足时间和路线。
但是总会有一些设计你可能需要处理最后几条路径。我会删除你所有的位置限制，并看看当你不想弄乱它时工具的效果如何（它可能做得很好）
。
如果设计需要loc和其他手持，则可能需要在FPGA Editor中进行手动布线。
如果您无法手动修复最后两条路径，则无需使用电线。互连矩阵特意稀疏，因为能够完全交叉点太昂贵（晶体管太多）。
Austin Lesea主要工程师Xilinx San Jose



以下为原文

m,

Looks like you ran out of paths, so it took a less optimal one.

The -verbose option will list all the paths, and their timings.

Wires have multiple places they get routed (re-used) so that "most" designs meet timing, and route.  But there will always be some designs you may have to work with for those last few paths.

I would remove all your location constraints, and see how well the tool does when you are not trying to mess with it (it may do just fine).  If the design require the loc's and other hand-holding, it may require hand routing in FPGA Editor.  If you can't fix these last two paths by hand, then there are no wires to use.

The interconnect matrix is purposely sparse, as being able to do a full cross-point would be too expensive (too many transistors).
Austin Lesea
Principal Engineer
Xilinx San Jose

谢谢您的回复。
:)
确实看起来确实如此。
但鉴于设计的规律性，我不明白为什么14个其他实例就像它没有这个问题...
-verbose选项到你指的是什么？
为了详细的帖子和地方
路线时间报告？
我启用了。
问题是，我可以看到失败的路径就好了。
但我无法看到它是否用完了某种类型的路由资源，然后不得不使用备份计划（更长的路由）。
真正有用的是有一些报告/工具/ tcl脚本，我可以用它来确定给定的切片（或互连矩阵）正在使用的内容。
然后，如果特定类型的路由资源在某个位置处于100％使用率，那么我知道这可能会导致路径变慢。
至于删除所有位置约束，这实际上就是我的开始。
但不幸的是，没有LOC约束的时间比这些约束更糟糕。
并不是设计不会路由，只是没有这些限制，放置不是最理想的。
所以主要的问题是，是否有任何工具可以生成有关路由资源使用情况的报告？
现在我在fpga编辑器中做了大量的点击以找出它发生了什么，但这相当耗时。
我想在fpga编辑器或fpga_edlin中可能有一些聪明的tcl代码，但我不知道那个聪明才会是什么。
任何想法非常感谢！



以下为原文

 
Thank you for your reply. :)It does indeed look like that. But given the regularity of the design, I don't understand why 14 other instances just like it do not have this problem...The -verbose option to what precisely are you refering to? To trce for the verbose post place & route timing report? I have that enabled. The thing is, I can see the failing paths just fine. But I cannot see if for example it ran out of a certain type of routing resource, and then had to use the backup plan (a longer route). What would really help is there was some report/tool/tcl script with which I could figure out for a given slice (or interconnect matrix) what is being used. Then if a certain type of routing resource is at 100% usage at a certain location, I know a lot faster that this is a potential cause for slower paths.As for removing all location constraints, that is actually how I started out. But unfortunately the timings without the LOC constraints are worse than with these constraints. It is not that the design won't route, it's just that without these constraints the placement is suboptimal.So the main question is, is there any tool that can generate a report on routing resource usage? For now I do a whole lot of clicking around in fpga editor to find out what it going on, but that is rather time consuming. I was thinking maybe some clever tcl code in fpga editor or fpga_edlin, but I have no idea what that cleverness would have to be. Any ideas much appreciated! 

约翰，都能跟得上。
这里没有简单的方法：FPGA_editor和穷举搜索是必需的。不，我不会解释为什么我们做我们做的事情（创建稀疏结构矩阵）。你已经尝试过使用max effort，min area，
最小延迟，综合类型和布局布线指令？
最小功率怎么样？
通常情况下，工具可以选择出于非常好的原因而做出非常好的事情（例如，最小区域=最佳速度）......
Austin Lesea主要工程师Xilinx San Jose



以下为原文

John,

Nope.  No easy way here:  FPGA_editor and an exhaustive search is required.

And, no, I am not going to explain why we do what we do (to create the sparse fabric matrix).

Have you already tried using the max effort, min area, min delay, types of synthesis and place and route directives?  What about min power?  Often the tools have options that do very good things for unintended reasons (min area = best speed, for example)...
Austin Lesea
Principal Engineer
Xilinx San Jose

Austin Lesea了解Xilinx FPGA（裸片）设计的细节，只有极少数人可以匹配。
你（和其他人）会很好地坚持奥斯汀所写的每一个字。
我将把我的两分钱加到奥斯汀的评论中。
如果您已经确定了一个设计拓扑结构，这种拓扑结构不适合优雅且充分保证的布局和布线，那么您（有过度简化的风险）有两个选择：
重新审视您的顶层设计和拓扑，追求对布局布线工具更“友好”的架构或数据流。
承诺手动原始映射，然后手动放置，最后手动路由干预，以实现您的预​​期设计拓扑（和时序余量）。
如果您决定采取第二条路径 - 提高人工干预水平 - 这里有一些宝贵的建议：在详细的手动实施中投入大量的汗水和眼泪之前，请确保您的设计经过验证和稳定。
设计的小（或大）改变可能需要撕掉并重新做一些艰苦的设计工作。
另一个问题：将设计重新定位到更大的设备是否会将您的设计重新划分为“运行自动化工具”以进行布局和布线？
如果是这种情况，那么您需要权衡较大FPGA的额外成本与手动设计实施的延迟和风险，这种风险正在盯着您。
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
搜索论坛（并搜索网页）以寻找类似的主题。
不要在多个论坛上发布相同的问题。
不要在别人的主题上发布新主题或问题，开始新的主题！5。
学生：复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。
提供有用的详细信息（请与网页，数据表链接）.7。
您的代码中的评论不需要支付额外费用。
我没有支付论坛帖子的费用。
如果我写一篇好文章，那么我一无所获。



以下为原文

Austin Lesea knows the details of Xilinx FPGA (die) design to a degree that very few people can match.  You (and others) would do well to hang onto every word Austin writes.
 
I'll add my two cents to Austin's comments.
 
When you have settled on a design topology which does not lend itself well to a graceful and amply-margined placement and routing, you have (at the risk of over-simplification) two options:
 

• Revisit your top-level design and topology, in the pursuit of an architecture or data flow which is more 'friendly' to the place and route tools.
  
• Commit yourself to manual primitive mapping, then manual placement, and finally manual routing intervention to achieve your intended design topology (and timing margins).
  

If you decide to take the 2nd path -- increasing levels of manual intervention -- here is a valuable bit of advice:  make sure your design is verified and stable before you invest massive amounts of sweat and tears in detailed manual implementation.  It is possible that small (or large) changes to the design will require ripping up and re-doing some of your painstaking design work.
 
Another question:  Does re-targeting the design to a larger device pull your design back into the category of 'run the automated tools' for place and route?  If this is the case, then you'll need to weigh the additional cost of the larger FPGA against the delay and risk of the manual design implementation which is staring you in the face.
 
-- Bob Elkind
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide.  Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts.  If I write a good post, then I have been good for nothing.

@Austin：
我担心这可能是fpga编辑时间......
“而且，不，我不会解释为什么我们做我们做的事情（创建稀疏的结构矩阵）。”
我不打算要求秘密成分......我想要的是斯巴达6设计的一些方法，以了解某个区域或某些网络，如果路由是一个问题。
我注意到在PlanAhead中有一个指标，正是我正在寻找的东西。
每个CLB的水平和垂直路由拥塞。
但是，当我尝试其中一个指标的“显示数据”时，它会显示“无指标数据”消息。
不幸的是，根据AR＃38879，spartan-6不支持此功能。
所以我正在寻找的那种功能确实存在于工具中，而不是斯巴达-6。
:(
至于map + par选项，我为Optimize Timings做了一个smartexplorer运行，让我们做24个策略。
然后我选择了最好的一个，并在迭代成本表的情况下再做一次。
然后我选择了最好的选择。
我最终选择的选项如下：
MAP_COST = 13
MAP_FLAGS + = -logic_opt on -ol high -xe n -t $（MAP_COST）-w -xt 0 -register_duplication on -r 4 -global_opt off
MAP_FLAGS + = -ir all -pr off -lc off-power off
MAP_FLAGS + = -mt 2 -detail
PAR_FLAGS + = -ol high -xe n
PAR_FLAGS + = -mt 4 -w
如上所述，大多数设计路线都很好。
整个低速部分，没问题。
大多数高速部分，没问题。
只是这两条路径。



以下为原文


@Austin:I was afraid it might be fpga editor time... 
"And, no, I am not going to explain why we do what we do (to create the sparse fabric matrix)." 
It's not my intention to ask for the secret ingredients... All I am looking for is some way for a spartan-6 design to know for a certain area or certain nets if routing is a problem. I noticed in PlanAhead there is a metric for precisely the sort of thing I was looking for. 
Horizontal and vertical routing congestion per CLB. However when I try "Show data" for one of those metrics, it displays a "No data for metric" message. Unfortunately according to AR# 38879 this feature is not supported for spartan-6. So the kind of feature I was looking for does exist in the tools, just not for spartan-6. :( 
As for the map + par options, I did a smartexplorer run for Optimize Timings and let is do 24 strategies. Then I picked the best one and did another run just iterating the cost table. I then picked the best option from that.The options I ended up with were as follows:
MAP_COST   = 13MAP_FLAGS += -logic_opt on -ol high -xe n -t $(MAP_COST) -w -xt 0 -register_duplication on -r 4 -global_opt offMAP_FLAGS += -ir all -pr off -lc off -power offMAP_FLAGS += -mt 2 -detailPAR_FLAGS += -ol high -xe nPAR_FLAGS += -mt 4 -w 

As said, most of the design routes just fine. The entire lower speed part, no problem. Most of the high speed part, no problem. Just these 2 paths.

@Bob：
好吧，我做了两点。
手动原始映射，是的。
完全有可能是我缺乏verilog技能导致这一点，但我发现通过在纸上绘制所有东西，手工优化然后实例化原语，我得到了更好的结果。
请注意，我只为高速部分的关键路径做到了这一点。
没有这样的关注，其余的都很好。
手动放置我认为我做得相当不错，但这可能是我对路由缺乏了解的地方。
据我了解，正确的位置是迄今为止对成功路由的最大影响。
现在假设我不知道在一定的路由延​​迟中我可以从切片A路由到切片B有多少东西，很可能我得到了几乎正确但不太正确的位置。
这里的问题是，我不知道如何改进...是否有关于路由资源的spartan-6文档？
或者也许某些工具如PlanAhead中的“水平和垂直路由拥塞每个CLB”指标适用于斯巴达-6？
与此同时，我确实整理了一个快速的perl + fpga_edline脚本来转储和分析我感兴趣的网络的路线。它相当粗糙，但已经帮助我找到了其他一些有趣的东西。
在该主题上，在fpga编辑器中，当您选择路径时，您将获得突出显示的路径。
然后你可以放大所有的段，它会给出一个（x，y）坐标+“OUTBOUND”，PINBOUNCE，SINGLE，DOUBLE，PINFEED，LUTINPUT等等。
现在我可以在fpga编辑器中查看整个switchbox，将（x，y）+标签放入电子表格等等，但如果有一些方法可以获得这些节点+坐标的列表，那就太好了。
我不认为这些是绝密的，因为fpga编辑器中的任何人都可以随时使用它们。
但我做了一些搜索，找不到列表或简单的方法来生成它。
有任何想法吗？
至于重定向到更大的设备，我确实尝试过，但这无助于满足改进时间。
在目前阶段，工具仍有足够的空间来完成他们的工作。
我想，对于设计中令人讨厌的部分，它只是“用当前工具不能轻易完成”的情况。
或者至少，我不知道如何在没有太多额外努力的情况下使用当前工具完成任务。



以下为原文

 
@Bob:
Well, I did a bit of both. Manual primitive mapping, yes. It is entirely possible that it is my lack of verilog skill that causes this, but I found that I got better results by drawing everything out on paper, handoptimize and then instantiate primitives. Mind you I only did that for the critical path of the high speed part. The rest is just fine without such attention. Manual placement I thought I had done reasonably well, but that is probably where my lack of understanding of the routing gets in the way. As I understand it, the correct placement is by far the largest influence on succesful routing. Now given that I don't know what to expect how many things I can route from slice A to slice B within a certain routing delay, it is well possible that I got the placement almost right but not quite right.
The problem here is, I don't know how to improve that ... Is there a piece of the spartan-6 documentation on the routing resources? Or maybe some tool like the "Horizontal and vertical routing congestion per CLB" metrics in PlanAhead that works for spartan-6?
In the meantime I did put together a quick perl + fpga_edline script to dump and analyze the routes for the nets I was interested in. It's rather crude but already helped me pinpointed some other fun stuff. On that subject, in fpga editor when you select a path you get the highlighted route. You can then zoom in on all the segments, and it will give a (x,y) coordinate + things like "OUTBOUND", PINBOUNCE, SINGLE, DOUBLE, PINFEED, LUTINPUT and such.
Now I could go over the entire switchbox in fpga editor, put the (x,y) + label into a spreadsheet etc etc, but it would be nice if there were some way to get a list of these nodes + coordinates. I don't think these would be top secret since they are readily available to anyone in fpga editor. But I did a bit of searching and couldn't find a list or easy way to generate this. Any ideas?
As for retargeting to a larger device, I did try that, but that doesn't help meet improve timings. At the current stage there is still plenty of room for the tools to do their thing. I guess that for the offending piece of the design it is just a case of "cannot be easily done with current tools". Or at least, I don't know how to get it done with the current tools without a lot of extra effort.

在第一篇文章中，您提到逻辑严格受RLOC，BEL和LOC约束，并且某些（相同的？）网络正确路由而某些网络没有。
如果这些网络都具有相同的引脚连接且引脚处于相同的相对位置，那么您可以从一个成功路由的网络捕获定向路由约束并将其应用于所有类似的网络
强制使用相同的路由结果。
定向路由约束在FPGA编辑器中从现有路由捕获，然后应用于UCF文件。
一旦应用约束，您将需要重新运行实现流程。



以下为原文

In the first post you mentioned that the logic is tightly constrained with RLOC, BEL and LOC constraints and that some of the (identical?) nets are routed properly and some not. If these nets all have the same pin connectivity and the pins are in the same relative position, then it would be possible for you to capture a Directed Routing constraint from one of the nets with a successful route and apply it to all of the similar nets to force the same routing result.
 
Directed Routing constraints are capture in FPGA Editor from existing routes and then applied in the UCF file. You will need to rerun the implementation flow once the constraints are applied.

逻辑确实是对规则结构的重复。
它是Y方向上3个切片的块的16倍（沿着进位链）。
其中14个块满足时序要求，2个不满足时序要求。
你提出了一个关于使用ROUTE约束的好处。
到目前为止，我希望避免使用它们。
但也许如果我尽量使用RLOC，BEL和LOC，我也可以一路走下去并使用ROUTE ......到现在为止我已经花了一些时间盯着路线，并得到一点点
感觉什么适合（路线方式）和什么不适合。
现在虽然启发式很好，但是一个告诉我路由的文档会让我更好。
所以...有关于斯巴达6的文档有哪些关于此的信息吗？
它很可能存在，但我设法错过了它。
基本上与“SLICEX包含4个LUT6,8个FF等”相同类型的信息。
但是就像“一个CLB开关盒包含诸如此类的QUAD，DOUBLEs，SINGLEs，BOUNCEACROSSes”



以下为原文


The logic is indeed a repetition of a regular structure. It is 16 times a block of 3 slices in the Y direction (along a carry chain). And 14 of these blocks meet timing, 2 don't. You raise a good point about using ROUTE constraints as well. Up until now I was hoping to avoid having to use those. But maybe if I go as far as to use RLOC, BEL and LOC, I might as well go all the way and use ROUTE as well...

By now I have spent a bit more time staring at routes, and getting a bit of a feel for what fits (route-wise) and what doesn't. Now while heuristics are nice, a document telling me about the routing would me even nicer. So ... is there a piece of documentation on the spartan-6 that has some information on this? It is quite possible it exists, but I managed to miss it. Basically the same type of information as "a SLICEX contains 4 LUT6, 8 FFs etc.". But then like "a CLB switchbox contains such-and-such QUADs, DOUBLEs, SINGLEs, BOUNCEACROSSes"

路线限制并不难使用。
它确实比手动路由更容易。
在线程的早期，您询问了拥塞分析工具。
PlanAhead有这样的功能。



以下为原文

Route constraints aren't difficult to use. It's certaining easier than manual routing. Earlier in the thread you asked about congestion analysis tools. PlanAhead has such a feature.