完善资料让更多小伙伴认识你,还能领取20积分哦, 立即完善>
你好
我添加了一个使用EDK 9.1计算DCT的自定义IP(创建和导入外设向导)。 当我尝试生成比特流文件时,我显示此错误: 错误:NgdBuild:604 - 逻辑块'core_dct_0 / core_dct_0 / USER_LOGIC_I / dct_inst' 类型'dct'无法解析。 引脚名称拼写错误会导致这种情况, 缺少edif或ngc文件,或类型名称的拼写错误。 符号'dct' 目标'virtex2p'不支持。 我尝试manysolutionin这个forumbut我找不到合适的人。 模块DCT的实例化是 --DCT模块实例化 组件dct是 港口 ( CLK:IN std_logic; RST:IN std_logic; xin:IN std_logic_vector(7 downto 0); dct_2d:OUT std_logic_vector(11 downto 0); rdy_out:OUT std_logic); 最终组件; signal dct_module_rst:std_logic; 信号dct_module_xin:std_logic_vector(7 downto 0); 信号dct_module_output:std_logic_vector(11 downto 0); 信号dct_module_rdy_out:std_logic; 开始 - 此处添加了USUS逻辑实现 dct1:dct 港口地图( CLK => Bus2IP_Clk, RST => dct_module_rst, xin => dct_module_xin, dct_2d => dct_module_output, rdy_out => dct_module_rdy_out); 请任何建议可以帮助我。 以上来自于谷歌翻译 以下为原文 Hi I have add a custom IP that calculate the DCT with EDK 9.1 (create and import peripheral wizard) . When I try to generate the bitstream file, I show this error:ERROR:NgdBuild:604 - logical block 'core_dct_0/core_dct_0/USER_LOGIC_I/dct_inst' with type 'dct' could not be resolved. A pin name misspelling can cause this, a missing edif or ngc file, or the misspelling of a type name. Symbol 'dct' is not supported in target 'virtex2p'. I try many solution in this forum but I don't find the right one. the instantiation of the module DCT is --DCT module instantiation component dct is PORT ( CLK : IN std_logic; RST : IN std_logic; xin : IN std_logic_vector(7 downto 0); dct_2d : OUT std_logic_vector(11 downto 0); rdy_out : OUT std_logic); end component; signal dct_module_rst: std_logic; signal dct_module_xin: std_logic_vector(7 downto 0); signal dct_module_output: std_logic_vector(11 downto 0); signal dct_module_rdy_out: std_logic; begin --USER logic implementation added here dct1: dct port map ( CLK => Bus2IP_Clk, RST => dct_module_rst, xin => dct_module_xin, dct_2d => dct_module_output, rdy_out => dct_module_rdy_out); Please any suggestion can help me. |
|
相关推荐
13个回答
|
|
你针对哪种技术?
Virtex-2pro是否有机会? 如果是这样,请仔细阅读错误消息。 ------------------------------------------“如果它不起作用 模拟,它不会在板上工作。“ 以上来自于谷歌翻译 以下为原文 Which technology are you targetting? Is it Virtex-2pro by any chance? If so, read the error message more carefully. ------------------------------------------ "If it don't work in simulation, it won't work on the board." |
|
|
|
我假设“dct”核心是dct.edf或dct.ngc。
使用ngdbuild命令行上的-sd开关确保它位于项目目录中或搜索目录中指定的目录中。 以上来自于谷歌翻译 以下为原文 I assume that the "dct" core is either dct.edf or dct.ngc. Make sure that it's in the project directory or in a dirctory specified in a search directory with the -sd switch on the ngdbuild command line. |
|
|
|
“您正在针对哪种技术?Virtex-2pro是否有机会?如果是这样,请仔细阅读错误消息。”
消息的这一部分仅表示“dct”不被识别为该设备系列的原语。 因为“dct”是一个不是问题的核心。 以上来自于谷歌翻译 以下为原文 "Which technology are you targetting? Is it Virtex-2pro by any chance? If so, read the error message more carefully." This part of the message just means that "dct" is not recognised as a primitive for that device family. Since "dct" is a core that's not an issue. |
|
|
|
|
|
|
|
大家好
拜托,我不明白你的解决方案。 为什么我应该找到dct.edf和dct.ngc。 在我的情况下,我应该生成位文件而不找到网表目录。 以上来自于谷歌翻译 以下为原文 hi all Please, I don't understand your solution. Why I should find dct.edf and dct.ngc . In my case I should generate the bit file without locate the directory of netlist. |
|
|
|
core_dct是使用CIP向导在项目中添加的自定义IP.DCT是user_logic.vhd中的一个组件
以上来自于谷歌翻译 以下为原文 core_dct is a custom IP that is add in the project with CIP wizard.DCT is a component in the user_logic.vhd |
|
|
|
DCT不是受支持的V2p原语。
该符号需要扩展为某种东西。 Ihttp://www.xilinx.com/itp/xilinx10/books/docs/virtex2p_hdl/virtex2p_hdl.pdf 以上来自于谷歌翻译 以下为原文 DCT isn't a supported V2p primitive. The symbol will need to be expanded to something. Ihttp://www.xilinx.com/itp/xilinx10/books/docs/virtex2p_hdl/virtex2p_hdl.pdf |
|
|
|
我将此组件的名称修改为dct_ip但仍存在相同的错误:
错误:NgdBuild:604 - 逻辑块'core_dct_0 / core_dct_0 / USER_LOGIC_I / dct_inst' 类型'dct_ip'无法解析。 引脚名称拼写错误会导致这种情况, 缺少edif或ngc文件,或类型名称的拼写错误。 符号'dct_ip' 目标'virtex2p不支持 以上来自于谷歌翻译 以下为原文 I modified the name of this component into dct_ip but the same error still exist: ERROR:NgdBuild:604 - logical block 'core_dct_0/core_dct_0/USER_LOGIC_I/dct_inst' with type 'dct_ip' could not be resolved. A pin name misspelling can cause this, a missing edif or ngc file, or the misspelling of a type name. Symbol 'dct_ip' is not supported in target 'virtex2p |
|
|
|
有任何建议请。
-------------------------------------------------- ---------------------------- - - - - - - - - - - - - - - - - -帮帮我 - - - - - - - - --------------------- -------------------------------------------------- ---------------------------- 以上来自于谷歌翻译 以下为原文 Any suggestion please. ------------------------------------------------------------------------------ ---------------------------------HELP------------------------------------- ------------------------------------------------------------------------------ |
|
|
|
您的系统上是否有一个名为DNS_ip.edf,dct_ip.edif,dct_ip.edn或dct_ip.ngc的EDIF或NGC文件?
此文件是否在ISE项目的搜索路径中? 此文件中的模块是否为“dct_ip”,并且端口名称是否与其他模块中使用的端口匹配? 其中一个被打破了。 只有你能提供答案。 ------您是否尝试在Google中输入问题? 如果没有,你应该在发布之前。太多结果? 尝试添加网站:www.xilinx.com 以上来自于谷歌翻译 以下为原文 Is there an EDIF or NGC file that is called dct_ip.edf, dct_ip.edif, dct_ip.edn or dct_ip.ngc on your system? Is this file within the search paths for your ISE project? Is the module that is in this file called "dct_ip" and do the port names matched the ports used in your other module? One of these is broken. Only you can provide the answer. ------Have you tried typing your question into Google? If not you should before posting. Too many results? Try adding site:www.xilinx.com |
|
|
|
想想重播,
我在谷歌搜索,我测试了很多解决方案,但我找不到合适的解决方案。 我在我的系统中找不到dct_ip.ngc,dct_ip.efd,dct_ip.edn但是我发现这个文件代表自定义IP的网表.lipip_dct_0_wrapper.ngc。 我不在设计中使用ISE,我只使用EDK 9.1和特别是XPS。 实际上,我使用创建和导入外设向导将IP core_dct添加为自定义IP。 我联合user_logic.vhd指示组件dct_ip的实例化 user_logic.vhd 40 KB 以上来自于谷歌翻译 以下为原文 Thinks for the replay, I search in Google and I test many solution but I don't find the right one. I don't find dct_ip.ngc,dct_ip.efd,dct_ip.edn in my system but I find ip_dct_0_wrapper.ngc this file represents the netlist of the custom IP. I don't use ISE in my design , I just use EDK 9.1 and specially XPS. In fact, I add the IP core_dct as a custom IP with create and import peripheral wizard. I joint user_logic.vhd that indicate the instantiation of the component dct_ip |
|
|
|
您可以下载user_logic.vhd但将其作为文本文件user_logic.txt打开
以上来自于谷歌翻译 以下为原文 you can download user_logic.vhd but open it as a text file user_logic.txt |
|
|
|
>我的系统中找不到dct_ip.ngc,dct_ip.efd,dct_ip.edn
那么这是你的问题。 >但是我findip_dct_0_wrapper.ngc此文件代表自定义IP的网表。 如果这是您的自定义代码的顶级,那么为什么顶级代码“ip_dct_0_wrapper”中的模块名称不是? >我在设计中不使用ISE,我只使用EDK 9.1 EDK是ISE的包装器。 如果您正在放置和布线您的设计,那么您正在使用ISE。 >我在谷歌搜索,我测试了很多解决方案,但我找不到合适的解决方案。 这是我帖子底部的通用签名行,并不针对您帖子中的任何特定内容。 ------您是否尝试在Google中输入问题? 如果没有,你应该在发布之前。太多结果? 尝试添加网站:www.xilinx.com 以上来自于谷歌翻译 以下为原文 > I don't find dct_ip.ngc,dct_ip.efd,dct_ip.edn in my system Then this is your problem. > but I find ip_dct_0_wrapper.ngc this file represents the netlist of the custom IP. If this is the top level of your custom code then why isn't the module name in your top level code "ip_dct_0_wrapper"? > I don't use ISE in my design , I just use EDK 9.1 EDK is a wrapper around ISE. If you are placing and routing your design you are using ISE. > I search in Google and I test many solution but I don't find the right one. This is a generic signature line at the bottom of my posts and not directed at anything specific in your post(s). ------Have you tried typing your question into Google? If not you should before posting. Too many results? Try adding site:www.xilinx.com |
|
|
|
只有小组成员才能发言,加入小组>>
2298 浏览 7 评论
2705 浏览 4 评论
Spartan 3-AN时钟和VHDL让ISE合成时出现错误该怎么办?
2192 浏览 9 评论
3274 浏览 0 评论
如何在RTL或xilinx spartan fpga的约束文件中插入1.56ns延迟缓冲区?
2336 浏览 15 评论
有输入,但是LVDS_25的FPGA内部接收不到数据,为什么?
611浏览 1评论
1670浏览 1评论
171浏览 1评论
637浏览 0评论
1823浏览 0评论
小黑屋| 手机版| Archiver| 电子发烧友 ( 湘ICP备2023018690号 )
GMT+8, 2024-9-11 10:13 , Processed in 1.505382 second(s), Total 100, Slave 83 queries .
Powered by 电子发烧友网
© 2015 bbs.elecfans.com
关注我们的微信
下载发烧友APP
电子发烧友观察
版权所有 © 湖南华秋数字科技有限公司
电子发烧友 (电路图) 湘公网安备 43011202000918 号 电信与信息服务业务经营许可证:合字B2-20210191