时间忽略参数困境

你好。
我希望有人可以解释我遇到的xilinx tiG时序约束问题。
我有一种情况，在我的设计（verilog）中，我已经定义了一组24位64位宽的寄存器。寄存器由软件读/写。
读写接口具有应用于读和写总线的TIG。
所有寄存器都驱动FPGA中的内部逻辑，并且该路径也是TIGed。
然而，控制寄存器中有2位在读/写路径中需要TIG但是没有用于驱动内部逻辑的TIG。
我已经从所有寄存器的输出设置了一个时间组，但控制寄存器有一个例外。
我将此时间组上的TIG设置为内部逻辑。
我在读写路径上也有一个TIG。
我查看PCF文件中指定的TIG，控件rgister完全TIGGED。
然后直接修改PCF文件的其他任何建议如何克服这个？
如果不清楚，请告诉我，我会举一个例子。（适用于xilinx 9,10和11）
谢谢
艾伦



以下为原文

Hi.

I am hoping someone can shed some light on this problem I am encountering with the xilinx TIG timing constraint. I have a situation where in my design (verilog) I have defined a bank of 24 registers 64 bits wide The registers are read/write by software. The read write interface has a TIG applied to both the read and write bus. All the registers drive internal logic in the FPGA and that path is also TIGed. There are however 2 bits in the control register that need a TIG in the read/write path but NO tig to drive the internal logic. I have setup a timegroup from the output of all the registers with an exception on the control register. I set a TIG on this Timegroup to internal logic. I also have a TIG on the read write path. I look at the TIG that is specified in the PCF file and the control rgister is fully TIGGED. Other then modifying the PCF file directly is there any suggestions as to how to overcome this?. Please let me know if this is not clear and I will come up with an example.(applies to xilinx 9, 10 and 11)

Thank You
Allan