如何在一个四核中使用两个gtx收发器用于两个极光ips

你好@ rajuponnaganti
看起来你试图在一个四核中使用两个GTXE2_COMMON块。
您必须使用一个GTXE2_COMMON块，因为您在一个块中使用两个GTX。
谢谢，
维奈
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以下为原文

Hi @rajuponnaganti
 
It looks like you are trying to use two GTXE2_COMMON blocks in one quad.
You have to use one GTXE2_COMMON block since you are using two GTXs from one block.
 
Thanks,
Vinay
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您应该将一个Aurora核心的共享逻辑配置为包含在核心中，并将第二个Aurora核心的共享逻辑配置在示例设计中。技术上，核心中具有共享逻辑的核心称为主，另一个称为从核
。
Master包含公共实例，并向slave提供gtrefclkout。请参阅http://www.xilinx.com/support/documentation/ip_documentation/aurora_64b66b/v10_0/pg074-aurora-64b66b.pdf的“共享逻辑”部分。
有关框图，请参见相同PG的图3-17，其中显示了主站和从站之间的互连。
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以下为原文

You should configure one Aurora core's shared logic to be included within the core and the second Aurora  core's shared logic to be included in the example design.

Technically, the core with shared logic in the core is called as master and the other is called as slave. Master contains common instantiation in it and provides the gtrefclkout to the slave.

Please refer to "Shared Logic" section of http://www.xilinx.com/support/documentation/ip_documentation/aurora_64b66b/v10_0/pg074-aurora-64b66b.pdf

Refer to Figure 3-17 of the same PG for block diagram showing the inter-connectivity between master and slave.-----------------------------------------------------------------------------------------------
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我看到了你的重复帖子-http：//forums.xilinx.com/t5/Implementation/QPLL-loc-constraints/mp/640380#M13011http：//forums.xilinx.com/t5/General-Technical-Discussion/problem
-in-using-two-GTX-Transceivers-X1Y0-and-X1Y1 / mp / 640350＃M34780请避免重复发帖。
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以下为原文

I saw duplicate posts from you-
http://forums.xilinx.com/t5/Implementation/QPLL-loc-constraints/m-p/640380#M13011
http://forums.xilinx.com/t5/General-Technical-Discussion/problem-in-using-two-GTX-Transceivers-X1Y0-and-X1Y1/m-p/640350#M34780

Please avoid duplicate posts.-----------------------------------------------------------------------------------------------
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我不是在使用vivado。
我正在使用ise 14.7，设备xc7vx485tboard vc707



以下为原文

i am not using vivado. i am using ise 14.7, device xc7vx485t
board vc707

不建议将ISE生成的Auroa核心与7系列设备一起使用。
请参考http://www.xilinx.com/support/answers/54146.html您需要在Vivado-1中生成两个内核。
Aurora 6466b核心，共享逻辑存在于核心（Master）.2。
示例设计中存在具有共享逻辑的Aurora 64b66b内核（Slave）。然后，您必须在ISE设计中实例化它们并连接http://www.xilinx.com/support/documentation图3-17中所示的时钟信号。
Master to Slave的/ip_documentation/aurora_64b66b/v10_0/pg074-aurora-64b66b.pdf。试试这个，如果你发现任何问题请告诉我。
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以下为原文

It is not recommended to use ISE generated Auroa core with 7-series devices. Please refer to http://www.xilinx.com/support/answers/54146.html

You need to generate two cores in Vivado-
1. Aurora 6466b core with Shared logic present in the core (Master).
2. Aurora 64b66b core with Shared logic present in the example design (Slave).

Then you have to instantiate them in your ISE design and connect the clock signals shown under Figure 3-17 of http://www.xilinx.com/support/documentation/ip_documentation/aurora_64b66b/v10_0/pg074-aurora-64b66b.pdf  of Master to Slave.

Try this and let me know if you see any issues.-----------------------------------------------------------------------------------------------
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正如你的建议，我创建了一个vivado项目并在流媒体中添加了两个ips。
我找不到任何四元选择aoption。
如图所示。您可以共享vivado的设计文件。
我对vivado很新。
而且我不了解vivado中极光示例设计中的重置逻辑。
需要指导？



以下为原文

as you suggested, i created project an vivado and added two ips in streaming. i couldn't find any quad selection aoption.
as shown in images.can you share deign files for vivado. i am very new to vivado. and i dibn't understand reset logic in aurora example design in vivado.
need guidance?

常见的是Aurora核心的一部分，它在核心中具有共享逻辑。
如果在设计中打开master core-aurora_64b66b_0的项目目录，则会找到名称为design_1_aurora_64b66b_0_0_support.v的文件，您可以在其中找到GTHE2_COMMON实例。您的连接看起来是正确的。
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以下为原文

The common is part of the Aurora core which has shared logic present in the core.

If you open the project directory of the master core-aurora_64b66b_0 in your design, you will find a file by name design_1_aurora_64b66b_0_0_support.v in which you can find  GTHE2_COMMON instantiation.

Your connections looks correct.-----------------------------------------------------------------------------------------------
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我在创建框图中创建了上面的项目。
如何将帧生成模块和ll添加到axi，axi到ll模块极光IPS。



以下为原文

I created above project in create block diagram. How to add frame gen module and ll to axi,axi to ll module aurora IPS.?

您需要为此程序框图生成包装器文件，然后将此包装器与frame_gen / frame_check模块一起添加到设计的顶层。您应该将此包装器文件视为Aurora核心顶级文件，并将其包含在您的设计中
。
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以下为原文

You need to generate the wrapper file for this block diagram and then add this wrapper along with frame_gen/frame_check modules in the top-level of the design.

You should treat this wrapper file as Aurora core top-level file and include this in your design.-----------------------------------------------------------------------------------------------
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