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我们最近把一个板从S25FL512S切换到S25FL256S/256KBIT扇区选项,并且注意到在一个大容量擦除或4SE命令之后,Flash将响应RDSR1命令,所有的比特都是第一次设置的,然后RSDR1的后续读取将正确地显示WIP位和写入。成功,错误位将是0等。我们从未在S25FL512S上看到这一点,代码基本上是相同的。
插入一些(2-3)虚拟读取的RDSR1似乎是工作作为一个工作,我们能够投票WIP后,第一个虚拟读取。 有时读取状态寄存器是正常的吗?因为所有位设置/闪存有时不驱动状态寄存器位(我们在MISO上有1K脉冲串)吗?大容量擦除和轮询RDSR1之间有最小等待时间吗?SPI频率为2.5MHz,模式0和模式3都是相同的。Flash是工厂默认设置。 谢谢, 雅各伯 以上来自于百度翻译 以下为原文 We recently switched a board from the S25FL512S to the S25FL256S / 256kbit sector option, and have noticed that after a Bulk Erase or 4SE command, the flash will respond to a RDSR1 command with all bits set the first time, and then subsequent reads of RDSR1 will correctly show the WIP bit and write success, error bits will be 0 etc. We never saw this on the S25FL512S, code is basically the same. Inserting a few (2-3) dummy reads of RDSR1 seems to be working as a work around, we're able to poll WIP after the first dummy read. Is it normal to sometimes read the status register as all bits set / will the flash not drive the status register bits sometimes (we do have 1k pullups on MISO)? Is there a minimum wait time between bulk erase and polling RDSR1? SPI frequency is 2.5MHz, both mode 0 and mode 3 act the same. Flash is factory default settings afaik. Thanks, Jacob |
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2个回答
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嗨,雅各伯,
请确认您的板上是否满足AC参数TCS、CSβ高时间(程序/擦除)=50ns。 这将是对你的问题的回答,“在大容量擦除和轮询RDSR1之间有一个最小等待时间吗?”. S25FL512S和S25FL256S具有相同的TCS参数,但是,如果时间是边缘的,您可能会看到设备到设备的变化(一些设备通过,一些设备失败)。 最好的问候, 尊礼 以上来自于百度翻译 以下为原文 Hi Jacob, Please verify if an AC parameter tCS, CS# High Time (Program/Erase) = 50ns, is satisfied in your board. This would be an answer to your question, "Is there a minimum wait time between bulk erase and polling RDSR1?". The S25FL512S and S25FL256S has same tCS parameter, however, if the timing is marginal, you may see the device to device variation (some devices pass and some devices fails). Best Regards, Takahiro |
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60user65 发表于 2018-9-25 19:59 好的,谢谢。原来在我们的SPI驱动程序中有一个以前未注意到的bug,它没有正确地释放NCS,所以这是NCS的定时问题。看起来现在正在工作。 以上来自于百度翻译 以下为原文 Ok, thanks. It turns out there was a previously un-noticed bug in our SPI driver that was not releasing nCS correctly, so it was a nCS timing issue. It looks like it is working now. |
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