输入捕获和输出比较来自错误源的时钟

我尝试使用PIC24F16KA304中的输入捕获模块来测量一系列脉冲的频率。我也尝试使用输出比较模块作为“额外”定时器。我计划忽略实际的输出引脚，只是使用中断。我的问题是，这两个模块都拒绝从其他定时器时钟。他们只会从内部循环时钟计时。如果我正确地理解了数据表（和参考手册），您应该能够使用ICTSEL位（用于输入捕获）和Octhell位（用于输出比较），并选择您想要使用的时钟源。但是无论我选择什么，模块总是在62.5NS（内部循环时钟）上增加。我尝试过使用不同的定时器、不同的比较/捕获模块，但似乎没有什么不同。我还检查了这个芯片的勘误表，我看不到任何可以应用的东西。我已经附加了我的“宏.Inc”文件。我已经用我的McRoWork的监视窗口验证了，但是我想我会把它们包括进去，这样你就可以运行这个代码了。



      以下为原文

    I am trying to use the Input Capture module in a pic24f16ka304 to measure the frequency of a series of pulses. I am also trying to use the Output Compare modules as "extra" timers. I plan to ignore the actual output pin, and just use the interrupt.

The problem I'm having is that both of these modules refuse to clock from other timers. They will only clock from the internal cycle clock. If I understand the datasheet (and reference manuals) correctly, you should be able to use the ICTSEL bits (for the Input Capture) and the OCTSEL bits (for the Output Compare) and pick which clock source you want to use. But no matter what I select, the modules always increment at 62.5nS (the internal cycle clock).

I've tried using different timers, different compare/capture modules, but nothing seems to make a difference. I have also checked the errata for this chip, and I don't see anything that would apply here.

I've attached my "macros.inc" file. I've already verified with the watch window that my macros work, but I figured I'd include them so that you can run this code if you want.

;------------------------------------------------------------------------------
; Processor Setup
;------------------------------------------------------------------------------
.include "p24F16KA304.inc"
.include "macros.inc"
.list


config __FOSCSEL,FNOSC_FRCPLL
config __FOSC,OSCIOFNC_OFF & FCKSM_CSDCMD
config __FWDT,FWDTEN_OFF
config __FICD,ICS_PGx2

.global __reset




.bss
placeholder: .space 2






.text

;RESET VECTOR -----------------------------------------------------------------------------
__reset:

  BTSS OSCCON, #LOCK ;wait for the PLL to lock
BRA $-2

CLR CLKDIV ;set frc postscaler to make a 32Mhz Fosc, 16Mhz Fcy, 62.5nS Tcy

;Stack Pointer Init ---
MOV #__SP_init,W15 ; Initalize the Stack Pointer
MOV #__SPLIM_init,W0 ; Initialize the Stack Pointer Limit Register
MOV W0,SPLIM ; (__SP_init & __SPLIM_init values are calculated by linker)
NOP ; Add NOP to follow SPLIM initialization
  


;PORT INITIALIZE -------------------------------------------------------------------------------------


CLR ANSA ;make all PORTA analog inputs digital
BCLR TRISC, #RC8 ;make the output compare pin an output

;------------------------------------------------------------------------------------------------------




;OUTPUT COMPARE INITIALIZE -----------------------------------------------------------------------------------------

CLR T1CON
MOV #16, W0 ;setup timer to interrupt every 1uS
MOV W0, PR1

CLR OC2R ;set OC period to 100uS
MOV #100, W0
MOV W0, OC2RS
mOCTSEL OC2CON1, #0b100 ;use TMR1 for clock source
mSYNCSEL OC2CON2, #0b11111 ;self sync
mOCM OC2CON1, #0b101 ;turn module on

BSET T1CON, #TON

;----------------------------------------------------------------------------------------------------------





;INPUT CAPTURE AND TIMERS INITIALIZE -----------------------------------------------------------------------------

;TIMER2 (IC1 time base) TMR2 rolls over every 50uS
MOV #800, W0
MOV W0, PR2

;IC1
MOV #0x0460, W0 ;run from Timer2, interrupt every 4th capture
MOV W0, IC1CON1
MOV #0x0000, W0 ;free run
MOV W0, IC1CON2
MOV #0x0003, W0 ;turn on module, capture every rising edge
IOR IC1CON1

BSET T2CON, #TON ;turn on the time base


;-------------------------------------------------------------------------------------------------------------------







main:


BRA $




.end

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macros.txt (2.41 KB) - downloaded 21 times