DM8148通过DVO2输出1080P BT1120到THS8200

你好；
       你可以参考一下 DVRRDK_04.01.00.02 的SDK；
       里面有ths8200的驱动参考和调用；
       DVRRDK_04.01.00.02/dvr_rdk/mcfw/src_linux/devices/ths8200/

ternence hsu 你好，
     谢谢，我这边去下载dvrrdk看看。 

ernence hsu 你好，
    我没找到DVRRDK整个包，现在参照能查到的资料配置DVO2和THS8200，接上显示器后，显示器显示识别到1080P/60，但是没有图像输出，整个是黑屏的（HDMI显示的正常图像）。测量了THS8200的vs_in、hs_in、vs_out、hs_out都有信号，看不出明显问题。这是还有哪没配置对么？  具体配置如下：
VDO2配置：（displaylink id为SYSTEM_LINK_ID_DISPLAY_0）：
pContext->deviceParams[VDIS_DEV_DVO2].enable = TRUE;
pContext->deviceParams[VDIS_DEV_DVO2].outputInfo.vencNodeNum = VDIS_VENC_DVO2;
pContext->deviceParams[VDIS_DEV_DVO2].outputInfo.aFmt = VDIS_A_OUTPUT_COMPOSITE;
pContext->deviceParams[VDIS_DEV_DVO2].outputInfo.dvoFidPolarity = VDIS_POLARITY_ACT_HIGH;
pContext->deviceParams[VDIS_DEV_DVO2].outputInfo.dvoVsPolarity = VDIS_POLARITY_ACT_HIGH;
pContext->deviceParams[VDIS_DEV_DVO2].outputInfo.dvoHsPolarity = VDIS_POLARITY_ACT_HIGH;
pContext->deviceParams[VDIS_DEV_DVO2].outputInfo.dvoActVidPolarity = VDIS_POLARITY_ACT_HIGH;
pContext->deviceParams[VDIS_DEV_DVO2].outputInfo.dvoFmt = VDIS_DVOFMT_DOUBLECHAN;
pContext->deviceParams[VDIS_DEV_DVO2].outputInfo.dataFormat = SYSTEM_DF_YUV422SP_UV;
pContext->deviceParams[SYSTEM_DC_VENC_HDMI].colorSpaceMode = VDIS_CSC_MODE_SDTV_GRAPHICS_Y2R;
pContext->deviceParams[VDIS_DEV_DVO2].colorSpaceMode = VDIS_CSC_MODE_SDTV_GRAPHICS_Y2R

THS8200配置如下：
ths8200_write(I2C_THS8200,0x03,0x01); // chip_ctl
ths8200_write(I2C_THS8200,0x04,0x00); // csc_ric1
ths8200_write(I2C_THS8200,0x05,0x00); // csc_rfc1
ths8200_write(I2C_THS8200,0x06,0x00); // csc_ric2
ths8200_write(I2C_THS8200,0x07,0x00); // csc_rfc2
ths8200_write(I2C_THS8200,0x08,0x00); // csc_ric3
ths8200_write(I2C_THS8200,0x09,0x00); // csc_rfc3
ths8200_write(I2C_THS8200,0x0A,0x00); // csc_gic1
ths8200_write(I2C_THS8200,0x0B,0x00); // csc_gfc1
ths8200_write(I2C_THS8200,0x0C,0x00); // csc_gic2
ths8200_write(I2C_THS8200,0x0D,0x00); // csc_gfc2
ths8200_write(I2C_THS8200,0x0E,0x00); // csc_gic3
ths8200_write(I2C_THS8200,0x0F,0x00); // csc_gfc3
ths8200_write(I2C_THS8200,0x10,0x00); // csc_bic1
ths8200_write(I2C_THS8200,0x11,0x00); // csc_bfc1
ths8200_write(I2C_THS8200,0x12,0x00); // csc_bic2
ths8200_write(I2C_THS8200,0x13,0x00); // csc_bfc2
ths8200_write(I2C_THS8200,0x14,0x00); // csc_bic3
ths8200_write(I2C_THS8200,0x15,0x00); // csc_bfc3
ths8200_write(I2C_THS8200,0x16,0x00); // csc_offset1
ths8200_write(I2C_THS8200,0x17,0x00); // csc_offset12
ths8200_write(I2C_THS8200,0x18,0x00); // csc_offset23
ths8200_write(I2C_THS8200,0x19,0x03); // csc_offset3
ths8200_write(I2C_THS8200,0x1A,0x00); // tst_cntl
ths8200_write(I2C_THS8200,0x1B,0x00); // tst_ramp_cntl
ths8200_write(I2C_THS8200,0x1C,0x03); // dman_cntl
ths8200_write(I2C_THS8200,0x1D,0x00); // dtg_y_sync1
ths8200_write(I2C_THS8200,0x1E,0x00); // dtg_y_sync2
ths8200_write(I2C_THS8200,0x1F,0x00); // dtg_y_sync3
ths8200_write(I2C_THS8200,0x20,0x00); // dtg_cbcr_sync1
ths8200_write(I2C_THS8200,0x21,0x00); // dtg_cbcr_sync2
ths8200_write(I2C_THS8200,0x22,0x00); // dtg_cbcr_sync3
ths8200_write(I2C_THS8200,0x23,0x23); // dtg_y_sync_upper
ths8200_write(I2C_THS8200,0x24,0x23); // dtg_cbcr_sync_upper
ths8200_write(I2C_THS8200,0x25,0x2C); // dtg_spec_a
ths8200_write(I2C_THS8200,0x26,0x58); // dtg_spec_b
ths8200_write(I2C_THS8200,0x27,0x2C); // dtg_spec_c
ths8200_write(I2C_THS8200,0x28,0x84); // dtg_spec_d
ths8200_write(I2C_THS8200,0x29,0x00); // dtg_spec_d1
ths8200_write(I2C_THS8200,0x2A,0xC0); // dtg_spec_e
ths8200_write(I2C_THS8200,0x2B,0x00); // dtg_spec_h_m***
ths8200_write(I2C_THS8200,0x2C,0x00); // dtg_spec_h_l***
ths8200_write(I2C_THS8200,0x2D,0x00); // dtg_spec_i_m***
ths8200_write(I2C_THS8200,0x2E,0x00); // dtg_spec_i_l***
ths8200_write(I2C_THS8200,0x2F,0x58); // dtg_spec_k_l***
ths8200_write(I2C_THS8200,0x30,0x00); // dtg_spec_k_m***
ths8200_write(I2C_THS8200,0x31,0x00); // dtg_spec_k1
ths8200_write(I2C_THS8200,0x32,0x58); // dtg_speg_g_l***
ths8200_write(I2C_THS8200,0x33,0x00); // dtg_speg_g_m***
ths8200_write(I2C_THS8200,0x34,0x05); // dtg_total_pixel_m***
ths8200_write(I2C_THS8200,0x35,0x20); // dtg_total_pixel_l***
ths8200_write(I2C_THS8200,0x36,0x00); // dtg_linecnt_m***
ths8200_write(I2C_THS8200,0x37,0x01); // dtg_linecnt_l***
ths8200_write(I2C_THS8200,0x38,0x86); // dtg_mode
ths8200_write(I2C_THS8200,0x39,0x30); // dtg_frame_field_m***
ths8200_write(I2C_THS8200,0x3A,0x00); // dtg_frame_size_l***
ths8200_write(I2C_THS8200,0x3B,0x20); // dtg_field_size_l***
ths8200_write(I2C_THS8200,0x3C,0x80); // dtg_vesa_cbar_size
ths8200_write(I2C_THS8200,0x3D,0x00); // dac_upper
ths8200_write(I2C_THS8200,0x3E,0x00); // dac1_test
ths8200_write(I2C_THS8200,0x3F,0x00); // dac2_test
ths8200_write(I2C_THS8200,0x40,0x00); // dac3_test
ths8200_write(I2C_THS8200,0x41,0x40); // csm_clip_gy_low
ths8200_write(I2C_THS8200,0x42,0x40); // csm_clip_bcb_low
ths8200_write(I2C_THS8200,0x43,0x40); // csm_clip_rcr_low
ths8200_write(I2C_THS8200,0x44,0x53); // csm_clip_gy_high
ths8200_write(I2C_THS8200,0x45,0x3F); // csm_clip_bcb_high
ths8200_write(I2C_THS8200,0x46,0x3F); // csm_clip_rcr_high
ths8200_write(I2C_THS8200,0x47,0x40); // csm_shift_gy
ths8200_write(I2C_THS8200,0x48,0x40); // csm_shift_bcb
ths8200_write(I2C_THS8200,0x49,0x40); // csm_shift_rcr
ths8200_write(I2C_THS8200,0x4A,0x08); // csm_mult_gy_m***
ths8200_write(I2C_THS8200,0x4B,0x00); // csm_mult_bcb_rcr_m***
ths8200_write(I2C_THS8200,0x4C,0x00); // csm_mult_gy_l***
ths8200_write(I2C_THS8200,0x4D,0x00); // csm_mult_bcb_l***
ths8200_write(I2C_THS8200,0x4E,0x00); // csm_mult_rcr_l***
ths8200_write(I2C_THS8200,0x4F,0x00); // csm_mode
ths8200_write(I2C_THS8200,0x50,0x00); // dtg_bp1_2_m***
ths8200_write(I2C_THS8200,0x51,0x00); // dtg_bp3_4_m***
ths8200_write(I2C_THS8200,0x52,0x00); // dtg_bp5_6_m***
ths8200_write(I2C_THS8200,0x53,0x00); // dtg_bp7_8_m***
ths8200_write(I2C_THS8200,0x54,0x00); // dtg_bp9_10_m***
ths8200_write(I2C_THS8200,0x55,0x00); // dtg_bp11_12_m***
ths8200_write(I2C_THS8200,0x56,0x00); // dtg_bp13_14_m***
ths8200_write(I2C_THS8200,0x57,0x00); // dtg_bp15_16_m***
ths8200_write(I2C_THS8200,0x58,0x00); // dtg_bp1_l***
ths8200_write(I2C_THS8200,0x59,0x00); // dtg_bp2_l***
ths8200_write(I2C_THS8200,0x5A,0x00); // dtg_bp3_l***
ths8200_write(I2C_THS8200,0x5B,0x00); // dtg_bp4_l***
ths8200_write(I2C_THS8200,0x5C,0x00); // dtg_bp5_l***
ths8200_write(I2C_THS8200,0x5D,0x00); // dtg_bp6_l***
ths8200_write(I2C_THS8200,0x5E,0x00); // dtg_bp7_l***
ths8200_write(I2C_THS8200,0x5F,0x00); // dtg_bp8_l***
ths8200_write(I2C_THS8200,0x60,0x00); // dtg_bp9_l***
ths8200_write(I2C_THS8200,0x61,0x00); // dtg_bp10_l***
ths8200_write(I2C_THS8200,0x62,0x00); // dtg_bp11_l***
ths8200_write(I2C_THS8200,0x63,0x00); // dtg_bp12_l***
ths8200_write(I2C_THS8200,0x64,0x00); // dtg_bp13_l***
ths8200_write(I2C_THS8200,0x65,0x00); // dtg_bp14_l***
ths8200_write(I2C_THS8200,0x66,0x00); // dtg_bp15_l***
ths8200_write(I2C_THS8200,0x67,0x00); // dtg_bp16_l***
ths8200_write(I2C_THS8200,0x68,0x00); // dtg_linetype1
ths8200_write(I2C_THS8200,0x69,0x00); // dtg_linetype2
ths8200_write(I2C_THS8200,0x6A,0x00); // dtg_linetype3
ths8200_write(I2C_THS8200,0x6B,0x00);// dtg_linetype4
ths8200_write(I2C_THS8200,0x6C,0x00); // dtg_linetype5
ths8200_write(I2C_THS8200,0x6D,0x00); // dtg_linetype6
ths8200_write(I2C_THS8200,0x6E,0x00); // dtg_linetype7
ths8200_write(I2C_THS8200,0x6F,0x00); // dtg_linetype8
ths8200_write(I2C_THS8200,0x70,0x60); // dtg_hlength_l***
ths8200_write(I2C_THS8200,0x71,0x00); // dtg_hdly_m***
ths8200_write(I2C_THS8200,0x72,0x02); // dtg_hdly_l***
ths8200_write(I2C_THS8200,0x73,0x03); // dtg_vlength_l***
ths8200_write(I2C_THS8200,0x74,0x00); // dtg_vdly_m***
ths8200_write(I2C_THS8200,0x75,0x03); // dtg_vdly_l***
ths8200_write(I2C_THS8200,0x76,0x00); // dtg_vlength2_l***
ths8200_write(I2C_THS8200,0x77,0x07); // dtg_vdly2_m***
ths8200_write(I2C_THS8200,0x78,0xFF); // dtg_vdly2_l***
ths8200_write(I2C_THS8200,0x79,0x00); // dtg_hs_in_dly_m***
ths8200_write(I2C_THS8200,0x7A,0x3D); // dtg_hs_in_dly_l***
ths8200_write(I2C_THS8200,0x7B,0x00); // dtg_vs_in_dly_m***
ths8200_write(I2C_THS8200,0x7C,0x03); // dtg_vs_in_dly_l***
ths8200_write(I2C_THS8200,0x82,0x5F); // pol_cntl
ths8200_write(I2C_THS8200,0x83,0x00); // cgms_header
ths8200_write(I2C_THS8200,0x84,0x00); // cgms_payload_m***
ths8200_write(I2C_THS8200,0x85,0x00); // cgms_payload_l***
//INCLUDE,THS8200_default_settings.inc // default values to be used unless later modified
ths8200_write(I2C_THS8200,0x04,0x81); // csc_r11
ths8200_write(I2C_THS8200,0x05,0xD5); // csc_r12
ths8200_write(I2C_THS8200,0x08,0x06); // csc_r31
ths8200_write(I2C_THS8200,0x09,0x29); // csc_r32
ths8200_write(I2C_THS8200,0x0A,0x04); // csc_g11
ths8200_write(I2C_THS8200,0x0C,0x04); // csc_g21
ths8200_write(I2C_THS8200,0x0E,0x04); // csc_g31
ths8200_write(I2C_THS8200,0x10,0x80); // csc_b11
ths8200_write(I2C_THS8200,0x11,0xBB); // csc_b12
ths8200_write(I2C_THS8200,0x12,0x07); // csc_b21
ths8200_write(I2C_THS8200,0x13,0x42); // csc_b22
ths8200_write(I2C_THS8200,0x16,0x14); // csc_offs1
ths8200_write(I2C_THS8200,0x17,0xAE); // csc_offs12
ths8200_write(I2C_THS8200,0x18,0x8B); // csc_offs23
// CSC setup - map YCbCr to FS RGB
ths8200_write(I2C_THS8200,0x19,0x15); // csc_offs3 - CSC not bypassed, under-/overflow protection on
ths8200_write(I2C_THS8200,0x1C,0x5B); // data_cntl - D1CLKO disabled, FSADJ1, 4:2:2 to 4:4:4 conversion,
// 1x up-sampling, BT.656 output disabled, 20-bit 4:2:2 input format
// output sync level amplitude control
ths8200_write(I2C_THS8200,0x1D,0x00); // dtg1_y_sync1_l*** (default)
ths8200_write(I2C_THS8200,0x1E,0x00); // dtg1_y_sync2_l*** (default)
ths8200_write(I2C_THS8200,0x1F,0x00); // dtg1_y_sync3_l*** (default)
ths8200_write(I2C_THS8200,0x23,0x2A); // dtg1_y_sync_m***
ths8200_write(I2C_THS8200,0x24,0x00); // dtg1_cbcr_sync_m***
// timing setup
ths8200_write(I2C_THS8200,0x27,0x00); // dtg1_spec_c
ths8200_write(I2C_THS8200,0x2A,0x00); // dtg1_spec_e_l***
ths8200_write(I2C_THS8200,0x32,0x00); // dtg1_speg_g_l***, needed? ***
ths8200_write(I2C_THS8200,0x36,0x00); // dtg1_fieldflip_linecnt_m*** (default)
ths8200_write(I2C_THS8200,0x37,0x01); // dtg1_linecnt_l*** (default)
ths8200_write(I2C_THS8200,0x38,0x89); // dtg1_mode - Generic SDTV mode
// CSM setup
ths8200_write(I2C_THS8200,0x4A,0xFC); // csm_gy_cntl_mult_m*** - G/Y multiply, shift, clip enabled
ths8200_write(I2C_THS8200,0x4B,0x44); // csm_mult_bcb_rcr_m***
ths8200_write(I2C_THS8200,0x4C,0xAC); // csm_mult_gy_l***
ths8200_write(I2C_THS8200,0x4D,0xAC); // csm_mult_bcb_l***
ths8200_write(I2C_THS8200,0x4E,0xAC); // csm_mult_rcr_l***
ths8200_write(I2C_THS8200,0x4F,0xFF); // csm_rcr_bcb_cntl - R/Cr and B/Cb multiply, shift, clip enabled
// discrete output sync control
ths8200_write(I2C_THS8200,0x71,0x00); // dtg2_hlength_m***_hdly_m*** (default)
ths8200_write(I2C_THS8200,0x72,0x08); // dtg2_hdly_l*** - 8 pixels
ths8200_write(I2C_THS8200,0x74,0x00); // dtg2_vlength1_m***_vdly1_m*** (default)
ths8200_write(I2C_THS8200,0x75,0x01); // dtg2_vdly1_l*** - 1 line
ths8200_write(I2C_THS8200,0x76,0x00); // dtg2_vlength2_l*** (default) - must be set to 0x00 for progressive modes
ths8200_write(I2C_THS8200,0x77,0x07); // dtg2_vlength2_m***_vdly2_m*** (default) - must be set to 0x07 for progressive modes
ths8200_write(I2C_THS8200,0x78,0xFF); // dtg2_vdly2_l*** (default) - must be set to 0xFF for progressive modes
////////////////////////////////////////////////////////////////////////////////

ths8200_write(I2C_THS8200,0x03,0x01); // chip_ctl - high DLL freq range
//timing setup
ths8200_write(I2C_THS8200,0x25,0x2C); // dtg1_spec_a 192
ths8200_write(I2C_THS8200,0x26,0x4E); // dtg1_spec_b Hfp - 2 = 88 - 2
ths8200_write(I2C_THS8200,0x28,0xCA); // dtg1_spec_d HS + Hbp = 44 + 148
ths8200_write(I2C_THS8200,0x2B,0x00); // dtg1_spec_h_m***
ths8200_write(I2C_THS8200,0x2F,0x4E); // dtg1_spec_k_l*** hfp - 2 = 88 - 2
ths8200_write(I2C_THS8200,0x30,0x00); // dtg1_spec_k_m***
ths8200_write(I2C_THS8200,0x34,0x08); // dtg1_total_pixel_m*** 2200 pixels
ths8200_write(I2C_THS8200,0x35,0x98); // dtg1_total_pixel_l***
ths8200_write(I2C_THS8200,0x39,0x44); // dtg1_frame_field_m*** 1125 lines
ths8200_write(I2C_THS8200,0x3A,0x65); // dtg1_frame_size_l***
ths8200_write(I2C_THS8200,0x3B,0x65); // dtg1_field_size_l***
//generic mode line type setup. Set dtg_bp2_m*** and l*** to 1126 (lines per frame + 1)
ths8200_write(I2C_THS8200,0x50,0x04); // dtg2_bp1_2_m***
ths8200_write(I2C_THS8200,0x59,0x66); // dtg2_bp2_l***
//discrete output sync control
ths8200_write(I2C_THS8200,0x70,0x2C); // dtg2_hlength_l*** 44 pixels
ths8200_write(I2C_THS8200,0x73,0x06); // dtg2_vlength_l***
//discrete input sync control
ths8200_write(I2C_THS8200,0x79,0x00); // dtg2_hs_in_dly_m***
ths8200_write(I2C_THS8200,0x7A,0x78); // dtg2_hs_in_dly_l*** 40 + Hfp = 40 + 88 = 104 pixels
ths8200_write(I2C_THS8200,0x7B,0x00); // dtg2_vs_in_dly_m***
ths8200_write(I2C_THS8200,0x7C,0x04); // dtg2_vs_in_dly_l***
ths8200_write(I2C_THS8200,0x82,0x1B); //0x3B); // dtg2_cntl, YPbPr mode, embedded syncs, +HS +VS
针对THS8200的0x82寄存器：DM8148 DVO2输出设置是VDIS_DVOFMT_DOUBLECHAN，也就是内嵌。但是THS8200的0x82寄存器如果设置为内嵌（0x3B），接上显示器会提示没有输出，所以这里ths8200的0x82寄存器在参考配置下修改为了0x1B

你好；
        你的display link 有配置数据输出到DVO2吗？

ternence hsu,
    我理解是创建的link就是对应到DVO2输出了，SYSTEM_LINK_ID_DISPLAY_0对应到HDMI，SYSTEM_LINK_ID_DISPLAY_1对应到DVO2，我将link id修改这两个都试过。 这个理解对吗？
    说道这个，有个地方我没理解到：link id设置为SYSTEM_LINK_ID_DISPLAY_0、SYSTEM_LINK_ID_DISPLAY_1，HDMI都有输出，这个和我理解的不符。

根据你上面的信息，我感觉你还是没有把数据配置输出到dvo2，dvo2的输出时序驱动是正常了，但是没有数据过来；
建议你查一个地方的配置：
        ipnc_rdk/ipnc_mcfw/mcfw/src_bios6/links_m3vpss/system/system_dctrl.c 中的 gSystem_dctrlTriDisplayConfig 
        display 的输出逻辑，进来的通道和出去的通道，和前面配置调用是否符合。

配置如下代码所示，那我前面配置需要配置成怎么样的呢？ vpss文档我也没完全理解透，所以不晓得啷个对应上呀，只是参照的demo例子。
#if defined(TI_814X_BUILD)
/* Display Controller Configuration */
/* To tie DVO2 and HDCOMP together refer following Mesh */
Vps_DcConfig gSystem_dctrlTriDisplayConfig = [
VPS_DC_USERSETTINGS, /* Use Case */
/* Edge information */
[
[VPS_DC_BP0_INPUT_PATH, VPS_DC_VCOMP_MUX] ,
[VPS_DC_VCOMP_MUX, VPS_DC_VCOMP],
[VPS_DC_CIG_NON_CONSTRAINED_OUTPUT, VPS_DC_HDMI_BLEND],
[VPS_DC_CIG_PIP_OUTPUT, VPS_DC_DVO2_BLEND] ,
[VPS_DC_SEC1_INPUT_PATH, VPS_DC_SDVENC_MUX] ,
[VPS_DC_SDVENC_MUX, VPS_DC_SDVENC_BLEND] ,
[VPS_DC_GRPX0_INPUT_PATH, VPS_DC_HDMI_BLEND] ,
[VPS_DC_GRPX0_INPUT_PATH, VPS_DC_DVO2_BLEND] ,
[VPS_DC_GRPX2_INPUT_PATH, VPS_DC_SDVENC_BLEND],

[VPS_DC_MAIN_INPUT_PATH, VPS_DC_VCOMP],
[VPS_DC_AUX_INPUT_PATH, VPS_DC_VCOMP_MUX],
[VPS_DC_BP1_INPUT_PATH, VPS_DC_SDVENC_MUX],
]
,
12,
/* VENC information */
[
/* Mode information */
[
[VPS_DC_VENC_HDMI, [FVID2_STD_1080P_60]
]
, /* 1080p30 is mode
* is overwritten
* later inside
* System_displayCtrlInit
*/
[VPS_DC_VENC_DVO2, [FVID2_STD_1080P_60]
]
, /* 1080p30 is mode
* is overwritten
* later inside
* System_displayCtrlInit
*/
[VPS_DC_VENC_SD, [FVID2_STD_NTSC]
]
]
,
(VPS_DC_VENC_HDMI | VPS_DC_VENC_DVO2), /* Tied VENC bit
* mask */
3u /* Number of VENCs
*/
]
];
#endif

ternence hsu 你好，
     我们目前8148的硬件是设计有4路输出：HDMI一路、DVO2-VOUT0-THS8200-VGA一路、DVO1-VOUT1-GV7600-SDI一路、SD-CVBS一路。 按照这个需求，gSystem_dctrlTriDisplayConfig 以及显示link需要怎么设计和配置对应参数呢？

     我按照如下理解的，但是目前只验证了HDMI，正在调试DVO2。
         HDMI和DVO1是同一个硬件部分，对应display linkid SYSTEM_LINK_ID_DISPLAY_0，HDMI能输出了，SDI应该也就能输出。
         DVO2对应display linkid SYSTEM_LINK_ID_DISPLAY_1,
         SD-CVBS对应display linkid SYSTEM_LINK_ID_DISPLAY_2。

ternence hsu 你好， 
    现在ths8200设置1080P，yuv422 独立外同步模式，能输出测试图形，但是正常情况下是黑的。 我也觉得是你前面说那样，很可能是DVO2没有图像输出，只有时序输出。但是怎么设置DVO2输出，还是没完全搞懂。 我使用IPNCRDK3.8，除了linkid 使用 SYSTEM_LINK_ID_DISPLAY_1，还需要修改哪些地方呢?

我觉得 你首先要判断是否有数据给到displaylink  看看统计的数据里 displaylink前一个link的数据处理

恩，谢谢，现在可以的了。是按照那个文档修改的。 

根据这个文档《2577.DM81xx_DVR_RDK_Display_Output_Configuration.pdf》