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我正在创建一个状态机来描述一些控制信号。 当我合成vhdl代码时,它无法识别状态机。 相反,它识别使用单热编码信号。 谁能帮我? 它是否可以作为状态机使用? 这是Synthesize的结果 ================================================== ======================= * HDL综合* ======================= ================================================== 执行双向端口解析...... 合成单位。 相关的源文件是“C:/ Users / SOFIA PONTE / Documents / BCI / Software / VHDL / CONTROLLER / controller.vhd”。 对信号使用单热编码。 找到1位寄存器用于信号。 找到1位寄存器用于信号。 找到1位寄存器用于信号。 找到8位寄存器用于信号。 找到1位寄存器用于信号。 找到1位寄存器用于信号。 找到1位寄存器用于信号。 找到8位寄存器用于信号。 找到了信号的2位向上计数器。 发现在线265处产生的信号的2位比较器较少。找到6位寄存器用于信号。 摘要:推断出1个计数器。推导出28个D型触发器。推荐1个比较器。单元合成。 ================================================== ======================= HDL综合报告 宏统计#计数器:12位递增计数器:1#寄存器:91位寄存器:66位寄存器:18位寄存器:2#比较器:12位比较器:1 ================================================== ======================= 这是我的代码(它也在attch) 库IEEE;使用IEEE.STD_LOGIC_1164.ALL;使用IEEE.STD_LOGIC_ARITH.ALL;使用IEEE.STD_LOGIC_UNSIGNED.ALL; - 使用IEEE.NUMERIC_STD.ALL; ----如果在此代码中实例化----任何Xilinx原语,则取消注释以下库声明.-- library UNISIM; - 使用UNISIM.VComponents.all; 实体控制器是端口(clk:在STD_LOGIC中; Rx_data_in:在STD_LOGIC_VECTOR中(7 DOWNTO 0); Rxfifo_EMPTY:在STD_LOGIC中; Rxfifo_VALID:在STD_LOGIC中; mosi_control:在STD_LOGIC中; miso_control:在STD_LOGIC中; Txfifo_FULL:在STD_LOGIC中; ReadFIFORx:out STD_LOGIC; START:out STD_LOGIC; spi_control:out STD_LOGIC; Rx_data_out:out STD_LOGIC_VECTOR(7 DOWNTO 0); reset:out STD_LOGIC; Data_nRW:out STD_LOGIC; en_mosi,en_miso:out STD_LOGIC); end controller; 架构控制器的行为是 --Registosparamáquinadeestadostype state_type是(idle,load,id_command,reset_st,mosi,miso); signal state_reg,state_next:state_type; - Registos geraissignal reset_reg:std_logic; signal set_mosi_out,load_done:STD_LOGIC; signal datareg_en,set_rd_flag, clr_rd_flag:std_logic; signal set_start,clr_start:std_logic; signal set_datanrw,clr_datanrw:std_logic; signal set_rdrx,clr_rdrx:std_logic; signal set_spi_cont,clr_spi_cont:std_logic; signal set_mosi,clr_mosi,set_miso,clr_miso:std_logic; signal mosi_count:std_logic_vector(1 downto 0);信号DATA:std_logic_vector(7 downto 0); begindatareg_en如果Rxfifo_EMPTY ='1'sostate_next elsif DATA =“00010000”thenstate_next elsif(Rxfifo_EMPTY ='1'和mosi_count state_next end if;当load => if load_done ='1'sostate_next end if if; when id_command => case DATA iswhen“ 00001000“=> - STARTstate_next时”00010000“=> - RDATACstate_next时”00001010“=> - STOPstate_next时”00000110“=> - RESETstate_next时其他=> state_next结束情况;当reset_st => state_next时mosi = >如果mosi_control ='1'sostate_next结束if;当miso => if miso_control ='1'sostate_next end if; end case; end process; OUT_SM:process(state_reg,Txfifo_FULL,Rxfifo_EMPTY,datareg_en,DATA,mosi_control,miso_control,mosi_count )beginreset_reg clr_start set_start clr_datanrw set_datanrw set_rdrx clr_rdrx set_spi_cont clr_spi_cont set_mosi_out set_rd_flag clr_rd_flag load_done set_mosi clr_mosi set_miso clr_miso情况state_reg iswhen空闲=>如果Rxfifo_EMPTY = '1' thenset_rdrx END IF;如果mosi_count = “10” thenclr_rd_flag END IF;当LO ad => if datareg_en ='1'henclr_rdrx load_done end if; when id_command => case DATA iswhen“00001000”=> - STARTset_start when“00010000”=> - RDATACset_mosi_out when“00001010”=> - STOPclr_start when“001XXXXX “=> set_mosi_out set_rd_flag当其他=> set_mosi_out结束情况;当reset_st => reset_reg时mosi =>如果mosi_control ='1'则clr_mosi clr_spi_cont如果mosi_count set_rd_flag结束if; elseclr_datanrw set_spi_cont set_mosi end if;当miso => if Txfifo_FULL =' 0'soset_miso else clr_miso end if;如果DATA =“00010000”thenset_datanrw else clr_datanrw end if if; if miso_control ='1'henclr_miso clr_spi_cont elseset_miso set_spi_cont end if if; end case; end process; 重启 controller.vhd 8 KB 以上来自于谷歌翻译 以下为原文 Hello! I'm traying to creat a state machine to describe some control signals. When I synthesize the vhdl code it doesn't recognize the state machine. Instead, it recognizes Using one-hot encoding for signal Here is the result of the Synthesize ========================================================================= * HDL Synthesis * ========================================================================= Performing bidirectional port resolution... Synthesizing Unit Related source file is "C:/Users/SOFIA PONTE/Documents/BCI/Software/VHDL/CONTROLLER/controller.vhd". Using one-hot encoding for signal Found 1-bit register for signal Found 1-bit register for signal Found 1-bit register for signal Found 8-bit register for signal Found 1-bit register for signal Found 1-bit register for signal Found 1-bit register for signal Found 8-bit register for signal . Found 2-bit up counter for signal Found 2-bit comparator less for signal Found 6-bit register for signal Summary: inferred 1 Counter(s). inferred 28 D-type flip-flop(s). inferred 1 Comparator(s). Unit ========================================================================= HDL Synthesis Report Macro Statistics # Counters : 1 2-bit up counter : 1 # Registers : 9 1-bit register : 6 6-bit register : 1 8-bit register : 2 # Comparators : 1 2-bit comparator less : 1 ========================================================================= Here is my code (it is also in attch) library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; --use IEEE.NUMERIC_STD.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity controller is Port ( clk : in STD_LOGIC; Rx_data_in : in STD_LOGIC_VECTOR (7 DOWNTO 0); Rxfifo_EMPTY : in STD_LOGIC; Rxfifo_VALID : in STD_LOGIC; mosi_control : in STD_LOGIC; miso_control : in STD_LOGIC; Txfifo_FULL : in STD_LOGIC; ReadFIFORx: out STD_LOGIC; START : out STD_LOGIC; spi_control: out STD_LOGIC; Rx_data_out : out STD_LOGIC_VECTOR (7 DOWNTO 0); reset : out STD_LOGIC; Data_nRW : out STD_LOGIC; en_mosi, en_miso: out STD_LOGIC); end controller; architecture Behavioral of controller is --Registos para máquina de estados type state_type is (idle, load, id_command, reset_st, mosi, miso); signal state_reg, state_next : state_type; --Registos gerais signal reset_reg : std_logic; signal set_mosi_out, load_done : STD_LOGIC; signal datareg_en, set_rd_flag, clr_rd_flag : std_logic; signal set_start, clr_start : std_logic; signal set_datanrw, clr_datanrw : std_logic; signal set_rdrx, clr_rdrx : std_logic; signal set_spi_cont, clr_spi_cont : std_logic; signal set_mosi, clr_mosi, set_miso, clr_miso : std_logic; signal mosi_count : std_logic_vector(1 downto 0); signal DATA: std_logic_vector (7 downto 0); begin datareg_en <= Rxfifo_VALID; -- DATA reg datareg: process(clk) begin if (rising_edge(clk) and datareg_en = '1') then DATA <= Rx_data_in; end if; end process; MOSIreg: process(clk) begin if rising_edge(clk) then if set_mosi = '1' then en_mosi <= '1'; elsif clr_mosi = '1' then en_mosi <= '0'; end if; end if; end process; MISOreg: process(clk) begin if rising_edge(clk) then if set_miso = '1' then en_miso <= '1'; elsif clr_miso = '1' then en_miso <= '0'; end if; end if; end process; startreg: process(clk, set_start, clr_start) begin if rising_edge(clk) then if set_start = '1' then START <= '1'; elsif clr_start = '1' then START <= '0'; end if; end if; end process; datanrwreg: process(clk, set_datanrw, clr_datanrw) begin if rising_edge(clk) then if set_datanrw = '1' then Data_nRW <= '1'; elsif clr_datanrw = '1' then Data_nRW <= '0'; end if; end if; end process; RdRx: process(clk, set_rdrx, clr_rdrx) begin if rising_edge(clk) then if set_rdrx = '1' then ReadFIFORx <= '1'; elsif clr_rdrx = '1' then ReadFIFORx <= '0'; end if; end if; end process; SPIcont: process(clk, set_spi_cont, clr_spi_cont) begin if rising_edge(clk) then if set_spi_cont = '1' then spi_control <= '0'; elsif clr_spi_cont = '1' then spi_control <= '1'; end if; end if; end process; DataMOSI: process(clk, set_mosi_out) begin if (rising_edge(clk) and set_mosi_out = '1') then Rx_data_out <= DATA; end if; end process; ReadFlag: process(clk, set_rd_flag, clr_rd_flag) begin if rising_edge(clk) then if set_rd_flag = '1' then mosi_count <= mosi_count + 1; elsif clr_rd_flag = '1' then mosi_count <= "00"; end if; end if; end process; -- Load do estado StateM: process(clk) begin if rising_edge(clk) then state_reg <= state_next; end if; end process; --Proximo Estado Next_SM: process(state_reg, Rxfifo_EMPTY, load_done, DATA, mosi_count, mosi_control, miso_control) begin state_next <= state_reg; case state_reg is when idle => if Rxfifo_EMPTY = '1' then state_next <= load; elsif DATA = "00010000" then state_next <= miso; elsif (Rxfifo_EMPTY = '1' and mosi_count < "10") then state_next <= load; end if; when load => if load_done = '1' then state_next <= id_command; end if; when id_command => case DATA is when "00001000" => -- START state_next <= idle; when "00010000" => -- RDATAC state_next <= mosi; when "00001010" => -- STOP state_next <= idle; when "00000110" => -- RESET state_next <= reset_st; when others => state_next <= mosi; end case; when reset_st => state_next <= idle; when mosi => if mosi_control = '1' then state_next <= idle; end if; when miso => if miso_control = '1' then state_next <= idle; end if; end case; end process; OUT_SM: process(state_reg, Txfifo_FULL, Rxfifo_EMPTY, datareg_en, DATA, mosi_control, miso_control, mosi_count) begin reset_reg <= '0'; clr_start <= '0'; set_start <= '0'; clr_datanrw <='0'; set_datanrw <='0'; set_rdrx <= '0'; clr_rdrx <= '0'; set_spi_cont <= '0'; clr_spi_cont <= '0'; set_mosi_out <= '0'; set_rd_flag <= '0'; clr_rd_flag <= '0'; load_done <= '0'; set_mosi <= '0'; clr_mosi <= '0'; set_miso <= '0'; clr_miso <= '0'; case state_reg is when idle => if Rxfifo_EMPTY = '1' then set_rdrx <= '1'; end if; if mosi_count = "10" then clr_rd_flag <= '1'; end if; when load => if datareg_en = '1' then clr_rdrx <= '1'; load_done <= '1'; end if; when id_command => case DATA is when "00001000" => -- START set_start <= '1'; when "00010000" => -- RDATAC set_mosi_out <= '1'; when "00001010" => -- STOP clr_start <= '1'; when "001XXXXX" => set_mosi_out <= '1'; set_rd_flag <= '1'; when others => set_mosi_out <= '1'; end case; when reset_st => reset_reg <= '1'; when mosi => if mosi_control = '1' then clr_mosi <= '1'; clr_spi_cont <= '1'; if mosi_count < "10" then set_rd_flag <= '1'; end if; else clr_datanrw <= '1'; set_spi_cont <= '1'; set_mosi <= '1'; end if; when miso => if Txfifo_FULL = '0' then set_miso <= '1'; else clr_miso <= '1'; end if; if DATA = "00010000" then set_datanrw <= '1'; else clr_datanrw <= '1'; end if; if miso_control = '1' then clr_miso <= '1'; clr_spi_cont <= '1'; else set_miso <= '1'; set_spi_cont <= '1'; end if; end case; end process; reset <= reset_reg; end Behavioral; controller.vhd 8 KB |
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“对信号使用单热编码”意味着合成器已检测到
使用“state_reg”作为其状态变量并且合成器已重新启动的状态机 每个状态使用一个触发器编码状态,或“一热”。 有开关 合成器使用其他编码,包括合成属性和属性 您可以附加到源代码。 FSM的默认合成属性“Auto” 编码允许它选择最佳的硬件实现。 用于机器 相对较少的州,通常是速度和面积的最佳选择 一热编码。 生成的硬件应该与原始硬件相同 编码,除非您遇到可能导致异步事件的问题 一台热门的机器来锁定二进制编码机器不会的位置。 HTH, 的Gabor - Gabor 以上来自于谷歌翻译 以下为原文 "Using one-hot encoding for signal a state machine using "state_reg" as its state variable and that the synthesizer has re- encoded the states using one flip-flop per state, or "one-hot". There are switches for the synthesizer to use other encodings, both in the synthesis properties and as attributes you can attach to your source code. The default synthesis property of "Auto" for FSM encoding allows it to choose the best hardware implementation. For machines with a relatively small number of states, the best choice for speed and area is usually one-hot encoding. The resulting hardware should behave the same as the original encoding, unless you have problems with asynchronous events that could cause the one-hot machine to lock up where a binary encoded machine would not. HTH, Gabor -- Gabor |
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