Pack无法将下面列出的符号组合到单个IOB组件中

您好，我是Xilinx的新手。
在实施期间，我在所有4个差分对上都会出现以下错误
：
错误：Pack：1107 - Pack无法将下面列出的符号组合到单个IOB组件中，因为所选的站点类型不兼容。
进一步说明：组件类型由逻辑类型及其包含的逻辑的属性和配置决定。
在这种情况下，选择类型为IOB的IO组件，因为IO包含与输入，输出或双向使用一致的符号和/或属性，并且不包含需要更具体的IO组件类型的其他符号或属性。
请仔细检查逻辑元素的类型及其所有相关属性和配置选项是否与约束的物理站点类型兼容。
摘要：涉及的符号：BUF符号“AG2_TX_P_IBUF”（输出信号= AG2_TX_P_IBUF）PAD符号“AG2_TX_P”（填充信号= AG2_TX_P）涉及的组件类型：涉及的IOB站点位置：涉及的AE19站点类型：OPAD
我正在使用Spartan 6（xc6lx75t-3fgg676）设备。
我的.uc文件看起来像这样：
## AG1 Fiber Optic1 NET AG1_RX_P LOC = AC20;
## NET AG1_RX_N LOC = AD20;
## NET AG1_TX_P LOC = AE21;
## NET AG1_TX_N LOC = AF21;
## NET AG1_FO_CLKLOC = AC22 |
IOSTANDARD = LVCMOS33;
NET AG1_FO_DATALOC = AF22 |
IOSTANDARD = LVCMOS33;
NET AG1_FO_LOSLOC = AA22 |
IOSTANDARD = LVCMOS33;
NET AG1_FO_PRESENTLOC = AB22 |
IOSTANDARD = LVCMOS33;
NET AG1_FO_TDISLOC = AB21 |
IOSTANDARD = LVCMOS33;
## AG2 Fiber Optic NET AG2_RX_P LOC = AC18;
## NET AG2_RX_N LOC = AD18;
## NET AG2_TX_P LOC = AE19;
## NET AG2_TX_N LOC = AF19;
## NET AG2_FO_CLKLOC = W17 |
IOSTANDARD = LVCMOS33;
NET AG2_FO_DATALOC = Y17 |
IOSTANDARD = LVCMOS33;
NET AG2_FO_LOSLOC = Y20 |
IOSTANDARD = LVCMOS33;
NET AG2_FO_PRESENTLOC = W18 |
IOSTANDARD = LVCMOS33;
NET AG2_FO_TDISLOC = AA17 |
IOSTANDARD = LVCMOS33;
## AG3 Fiber Optic NET AG3_RX_P LOC = AC10;
## NET AG3_RX_N LOC = AD10;
## NET AG3_TX_P LOC = AE9;
## NET AG3_TX_N LOC = AF9;
## NET AG3_FO_CLK LOC = W7 |
IOSTANDARD = LVCMOS33;
NET AG3_FO_DATA LOC = AA7 |
IOSTANDARD = LVCMOS33;
NET AG3_FO_LOS LOC = AA9 |
IOSTANDARD = LVCMOS33;
NET AG3_FO_PRESENT LOC = W8 |
IOSTANDARD = LVCMOS33;
NET AG3_FO_TDIS LOC = AA6 |
IOSTANDARD = LVCMOS33;
## AG4 Fiber Optic NET AG4_RX_P LOC = AC8;
## NET AG4_RX_N LOC = AD8;
## NET AG4_TX_P LOC = AE7;
## NET AG4_TX_N LOC = AF7;
## NET AG4_FO_CLK LOC = AC5 |
IOSTANDARD = LVCMOS33;
NET AG4_FO_DATA LOC = AD5 |
IOSTANDARD = LVCMOS33;
NET AG4_FO_LOS LOC = AD6 |
IOSTANDARD = LVCMOS33;
NET AG4_FO_PRESENT LOC = AF6 |
IOSTANDARD = LVCMOS33;
NET AG4_FO_TDIS LOC = AD4 |
IOSTANDARD = LVCMOS33;
NET CLK_124M_0_N LOC = AF17;
NET CLK_124M_0_P LOC = AE17;
NET CLK_124M_1_N LOC = AD16;
NET CLK_124M_1_P LOC = AC16;
NET CLK_124M_2_N LOC = AD12;
NET CLK_124M_2_P LOC = AC12;
NET CLK_124M_3_N LOC = AF11;
NET CLK_124M_3_P LOC = AE11;
NET“CLK_124M_0_N”TNM_NET = GTP_CLK_124M_0_N; TIMESPEC TS_GTP_CLK_124M_0_N = PERIOD“GTP_CLK_124M_0_N”8.03729 ns HIGH 50％;
NET“CLK_124M_0_P”TNM_NET = GTP_CLK_124M_0_P; TIMESPEC TS_GTP_CLK_124M_0_P = PERIOD“GTP_CLK_124M_0_P”8.03729 ns HIGH 50％;
NET“CLK_124M_1_N”TNM_NET = GTP_CLK_124M_1_N; TIMESPEC TS_GTP_CLK_124M_1_N = PERIOD“GTP_CLK_124M_1_N”8.03729 ns HIGH 50％;
NET“CLK_124M_1_P”TNM_NET = GTP_CLK_124M_1_P; TIMESPEC TS_GTP_CLK_124M_1_P = PERIOD“GTP_CLK_124M_1_P”8.03729 ns HIGH 50％;
NET“CLK_124M_2_N”TNM_NET = GTP_CLK_124M_2_N; TIMESPEC TS_GTP_CLK_124M_2_N = PERIOD“GTP_CLK_124M_2_N”8.03729 ns HIGH 50％;
NET“CLK_124M_2_P”TNM_NET = GTP_CLK_124M_2_P; TIMESPEC TS_GTP_CLK_124M_2_P = PERIOD“GTP_CLK_124M_2_P”8.03729 ns HIGH 50％;
NET“CLK_124M_3_N”TNM_NET = GTP_CLK_124M_3_N; TIMESPEC TS_GTP_CLK_124M_3_N = PERIOD“GTP_CLK_124M_3_N”8.03729 ns HIGH 50％;
NET“CLK_124M_3_P”TNM_NET = GTP_CLK_124M_3_P; TIMESPEC TS_GTP_CLK_124M_3_P = PERIOD“GTP_CLK_124M_3_P”8.03729 ns HIGH 50％;
我的顶级vhdl只在实体顶层声明了这些输入，并且当前没有连接到任何东西。
- 光纤1 AG1_RX_P：IN STD_LOGIC;
AG1_RX_N：IN STD_LOGIC;
AG1_TX_P：IN STD_LOGIC;
AG1_TX_N：IN STD_LOGIC;
- 光纤2 ......
- 光纤3 ......
- 光纤4 ......
任何帮助是极大的赞赏。
谢谢，
Admir M.