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李铭冠

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[问答]

是否该强制使用DCM复位?

嗨,
我已经使用FPGA工作了几年,但我还没有意识到是否强制使用DCM复位。
我正在开发SP6,ISE14.7上的代码。
到目前为止,我曾经使用下面的电路 - 在VHDL中 - 有或没有检查和控制DCM_LOCK输出!
我真的很感激任何建议。
提前致谢,
侯赛因

以上来自于谷歌翻译


以下为原文

Hi,
I have been working for some years with FPGAs, but I've not yet realized if using DCM reset is mandatory or not. I am developing my code on SP6, ISE14.7. Until now, I used to use below circuit - in VHDL - with or without checking and controlling DCM_LOCK output!.


I would really appreciate any advice.
Thanks in advance,
Hossein

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姚庭芳

2019-7-26 14:43:38
你好Hossein,
请访问以下链接:http://www.xilinx.com/support/troubleshoot/clocking_debug.htm
它会帮助你。
我的建议是使用RESET信号,
谢谢,
维奈
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以上来自于谷歌翻译


以下为原文

Hello Hossein,
 
Check this link: http://www.xilinx.com/support/troubleshoot/clocking_debug.htm
It will help you.
 
My suggestion is to use RESET signal,
 
Thanks,
Vinay
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潘晶燕

2019-7-26 14:54:12
另外,
有LOCKED信号和CLOCK_LOST信号(状态位)。
如果LOCKED丢失(变为假)或CLOCK LOST变为true,则应重置DCM。
通常,如果时钟在同一块板上(晶体ocsillator封装)并且它是如此可靠,并且检查LOCKED和CLOCK LOST是不必要的(因为它永远不会失锁,永远不会丢失时钟)。
但是,如果所有时钟都有可能出现故障或丢失,则需要在这些事件上重置DCM才能使DCM运行并再次锁定。
Austin Lesea主要工程师Xilinx San Jose

以上来自于谷歌翻译


以下为原文

Additionally,
 
There is the LOCKED signal, and CLOCK_LOST signal (status bits).  If LOCKED is lost (becomes false), or CLOCK LOST becomes true, you should reset the DCM.
 
Often if the clock is on the same board (crystal ocsillator package) and it is so reliable, and checking LOCKED and CLOCK LOST is not necessary (as it never loses lock, and never loses the clock).

But, if there is any chance at all the clock could glitch, or be lost, then reseting the DCM on those events is required to get the DCM running and locked again.
 
 
Austin Lesea
Principal Engineer
Xilinx San Jose
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