请问有几个GTP可以与usrclk2共享DCM

嗨，
您可以使用您提到的配置。
但是，还有另一面，当您为所有GTP使用相同的TXUSRCL时，您可能会看到时序违规。
请对用户时钟应用时序约束，看看是否可以满足时序要求。
问候，
克里希纳
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以下为原文

Hi,
 
You can use the configuration that you mentioned. But, there is a flip side to it, you may see timing violations when using the same TXUSRCLks for all GTPs.
 
Please apply timing constraints on the user clocks and see if you can meet the timing.
 
Regards,
Krishna
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克里希纳，
谢谢。
我将时序约束添加到双tile0_GTP0的gtpclkout0（0/1）。
refclk是148.5 MHz（因此usrclk20将是74.25 MHz）并且约束条件满足。
仍然从tile0_GTP1收到的数据有错误。
我观察到的另一件事是我不能使用gtpclkout0（0）来生成rxusrclk20，但是我可以使用rxrecclk0而不是gtpclkout0（1）来生成rxusrclk20并正确地从tile0_GTP0恢复数据。
问候，
马兹



以下为原文

Krishna,
 
Thanks. I added timing constraint to gtpclkout0(0/1) of the dual tile0_GTP0. The refclk is 148.5 MHz (and so the usrclk20 will be 74.25 MHz) and the constraints meet. Still the data received from tile0_GTP1 has errors.
 
Another thing that I observed was that I cannot use gtpclkout0(0) to generate rxusrclk20, but I can use rxrecclk0 instead of gtpclkout0(1) to generate rxusrclk20 and recover data from tile0_GTP0 correctly.
 
Regards,
Maz

gtpclkout0（0）用于Tx，gtpclkout0（1）用于Rx。
你发现设计在模拟中工作吗？
如果您使用逗号对齐，请检查此模块的状态信号以开始。
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以下为原文

gtpclkout0(0) is for Tx and gtpclkout0(1) is for Rx.

Do you find the design working in simulation? if you are using comma alignment, check the status signals of this module to start with.------------------------------------------------------------------------------
Don't forget to reply, give kudo and accept as solution
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Srinadh，
谢谢。
gtpclkout0（0）用于Tx，gtpclkout0（1）用于Rx。
来自UG386，
据说REFCLKPLL可以通过gtpclkout0（0）输出到FPGA逻辑，但你是对的。
如果我们“只”考虑频率，那么这个时钟与我设计中的rxrecclk相同。
你发现设计在模拟中工作吗？
如果您使用逗号对齐，请检查此模块的状态信号以开始。
是的，tile0_gtp1在使用gtpclkout0（1）和rxrecclk0（我不确定我检查了gtoclkout0（0））的模拟中效果很好。
没有我的设计没有逗号对齐。
我正在使用基于逻辑的DRU和框架......当我使用每个GTP的gtpclkout（1）时，一切都没问题，但我不能与其他GTP共享一个GTP的gtpclkout（1），即使所有线路速率和clks都是
一样。
问候，
马兹



以下为原文

Srinadh,
Thanks.

gtpclkout0(0) is for Tx and gtpclkout0(1) is for Rx.

From UG386,
 

It is said that REFCLKPLL can be ouput to FPGA logic via gtpclkout0(0), But you are right. If we "only" consider the frequency this clock is the same as rxrecclk in my design.
 

Do you find the design working in simulation? if you are using comma alignment, check the status signals of this module to start with.

Yes the tile0_gtp1 works well in simulation with gtpclkout0(1) and rxrecclk0 (I am not sure I checked the gtoclkout0(0)).


And no my desing doesn't have comma alignment. I am using a logic based DRU and framing and .... Everything is okay when I use each GTP's gtpclkout(1), but I cannot share one GTP's gtpclkout(1) with other GTPs, even though all the line rates and clks are the same.
 
Regards,
Maz