我需要产生一组视频像素时钟--27 MHz,74.25,148.5 MHz,297 MHz,并且每个Clk速率从Clk切换到Clk / 1.001。
在之前的项目中(Spartan 3 - 限制为148.5 MHz max Clk)我使用单个DCM从两个外部时钟(74.25 MHz和74.25 / 1.001 MHz)产生所有必需的Clk速率。
对于一个新项目,我使用的是Spartan 6,并且想考虑使用单个外部时钟来获得Clk和Clk / 1.001速率,但这需要一长串DCM和PLL。
特别,
27 MHz外部CLk - > DCM0 - > DCM1 - > PLL0产生74.25 MHz和74.25 / 1.001 MHz时钟。
然后
74.25 MHz和74.25 / 1.001 MHz时钟 - > PLL1产生所有必需的视频clks。
时钟向导将每个DCM / PLL的单个抖动报告为
DCM0 - 213 ps,DCM1 - 221 ps,PLL0 - 182 ps,PLL1 - 158 ps
任何人都可以建议我是否可以期待这个2 DCM&
2 PLL链可用于视频吗?
我是否期望抖动是4个分量(390 ps)的平方和的平方根?
或者在级联结束时使用PLL来清除先前PLL和放大器的一些抖动。
DCM可以产生更低的抖动?
以上来自于谷歌翻译
以下为原文
I need to produce a set of video pixel clocks - 27 MHz, 74.25, 148.5 MHz, 297 MHz and switch from Clk to Clk/1.001 for each Clk rate.
In previous projects (Spartan 3 - limited to 148.5 MHz max Clk) I've used a single DCM to produce all the necessary Clk rates fed from two external clocks (74.25 MHz and 74.25/1.001 MHz). For a new project I'm using a Spartan 6 and would like to consider using a single external clock to get both Clk and Clk/1.001 rates, but that requires a long cascade of DCM's and PLLs. Specifically,
27 MHz external CLk -> DCM0 -> DCM1 -> PLL0 produces both 74.25 MHz and 74.25/1.001 MHz clocks.
then
74.25 MHz and 74.25/1.001 MHz clocks -> PLL1 produces all required video clks.
The Clock Wizard reports the individual jitter for each DCM/PLL as
DCM0 - 213 ps, DCM1 - 221 ps, PLL0 - 182 ps, PLL1 - 158 ps
Can anyone advise if I could expect the jitter at the end of this 2 DCM & 2 PLL chain to be usable for video? Would I expect the jitter to be the square root of the sum of the squares of the 4 components (390 ps)? Or do the PLL's at the end of the cascade clean up some of the jitter of the previous PLL & DCM's to produce lower jitter?