如何避免冻结DCM？

你不需要BUFGMUX，只需要一个IBUFG。
问题是，如果你没有在时钟爆发到多个BUFG / DCM组件之前自己实例化，那么工具将会出错，因为它们最终会推断出多个输入缓冲区。
如果您想使用时钟向导，您有两种选择：
1）在其中一个时钟向导模块中，使用“单端”作为时钟输入，并将IBUFG的输出带到该模块的输出端口。
然后其他BUFG或DCM将使用来自输入缓冲区的时钟而无需进一步缓冲（即，如果您有另一个时钟向导模块，则需要使用“内部”作为时钟输入，因此它不会添加另一个IBUFG）。
2）将所有时钟向导模块设置为使用“internal”作为时钟源，然后在代码的顶层实例化IBUFG。
使用IBUFG的输出来驱动复位发生器的BUFG以及使用相同时钟输入工作的任何DCM。
您不能做的是直接从输入引脚网络扇出，因为工具将推断出多个输入缓冲区。
-  Gabor
在原帖中查看解决方案



以下为原文

You don't need a BUFGMUX, just an IBUFG.  The problem is that if you don't instantiate it yourself before the point where the clock breaks out into multiple BUFG / DCM components, then the tools will error out because they ill end up inferring more than one input buffer.
 
If you want to use the clocking wizard you have two choices:
 
1) in one of your clock wizard modules, use "Single-ended" as the clock input, and bring the output of the IBUFG to an output port of that module.  Then other BUFG or DCMs would use that clock from the input buffer without further buffering (i.e. if you have another clocking wizard module it would need to use "Internal" as the clock input so it doesn't add another IBUFG).
 
2) Set all clocking wizard modules to use "internal" as the clock source, then instantiate the IBUFG at the top level of your code.  Use the output of the IBUFG to drive the BUFG for the reset generator as well as any DCMs that work from the same clock input.
 
What you can't do is have fan-out directly from the input pin net because the tools will infer multiple input buffers.
-- GaborView solution in original post

在导致其失锁的时钟事件后，DCM不会自动重新获得锁定。
它需要重置。
我通常会添加一个重置控制器来执行此操作。
复位控制器必须运行的时钟不是它正在复位的DCM的输出。
在您的情况下，它可能是来自引脚的输入时钟通过额外的BUFG，或者您可以使用50 MHz系统的现有时钟。
其余控制器的想法是，当DCM锁定且DCM状态显示输入时钟正常运行时，您有一个计数器保持在复位状态。
否则它会计数。
允许终端计数回绕到零（这很重要）。
然后，当计数器大于某个值（通常接近终端计数）时，DCM的复位被置位。
计数器应足够大，以便在最坏情况锁定时间的数据表时间结束后才能重置DCM。
如果锁定时间太长，这会阻止它不断重置DCM。
显然，DCM的输出将无法使用，并且您可能还需要重置DCM下游的其他电路。
但是，如果您的系统能够容忍，那么它仍然比重新加载比特流更好。
-  Gabor



以下为原文

The DCM will not automatically re-gain lock after a clock event that causes it to lose lock.  It needs to be reset.  I normally add a reset controller to do this.  The reset controller must run on a clock that is not the output of the DCM it is resetting.  In your case it could be the input clock from the pin via an additional BUFG, or you could use an existing clock from the 50 MHz system.
 
The idea of the rest controller is that you have a counter which is held in reset when the DCM is locked and the DCM status shows that the input clock is running normally.  Otherwise it counts up.  At terminal count is allowed to wrap back to zero (this is important).  Then the reset of the DCM is asserted when the counter is greater than some value, usually near the terminal count.  The counter should be large enough that it doesn't reset the DCM until after the data sheet time for worst case lock time has elapsed.  That prevents it from constantly resetting the DCM if it takes too long to lock.
 
Obviously there will be some time period when that DCM's output is unusable, and you may also need to reset other circuitry downstream of the DCM.  However if your system can tolerate that, it's still better than re-loading the bitstream.
-- Gabor

你好Gabor，
谢谢你的回答。
所以不建议使用dcm的clock0输出来做你建议的。
如果我很好理解，即使该线在锁定时停止也会停止。
这是对的吗？
我试图限制fpga电路的复位，避免丢失系统状态并自动恢复
我想只重置通信寄存器
克劳迪奥



以下为原文

Hello Gabor,
thank you for your anwer.
So it is not recommended to use the clock0 output of the dcm to do what you suggested. If I well understand, even that line is stopped when lock is down. Is it correct?
 
My though is to try to limit the reset of the fpga circuitry avoiding to lose the status of the system and recover it automatically
I would like to reset only the communication registers
 
Claudio

锁定时，CLK0输出可能会发生转换，但复位输入有效时不会发生转换。
因此，如果将CLK0用于向DCM生成复位信号的状态逻辑，则一旦复位信号被置位，它就会被卡住。
另请注意，当锁定置为无效时，任何DCM输出的时序都可能超出约束条件（较短的脉冲宽度或较高的频率）。
-  Gabor



以下为原文

There can be transitions on the CLK0 output when lock is down, but not while the reset input is active.  So if you use CLK0 for the state logic that generates the reset signal to the DCM it will get stuck as soon as the reset signal is asserted.  Also note that any DCM outputs may have timing that is outside of your constraints (shorter pulse width or higher frequency) while lock is deasserted.
-- Gabor