如何解决Spartan 3A状态机出错问题？

枚举类型中的名称是该类型的本地名称，因此可以在其他类型中重复使用它们。
你展示的是完全合法的。
你说你有“奇怪的问题”。
什么类型的问题，为什么你怀疑STATE和STATE2的值有问题？
-  Gabor



以下为原文

The names in an enumerated type are local to that type, so it is fine to re-use them in another type.  What you showed is perfectly legal.
 
You said you are having "weird issues."  What sort of issues, and why do you suspect something wrong with the values of STATE and STATE2?
-- Gabor

谢谢G，
你回复我50％以上的问题:)。
我有非常奇怪的问题，我的工程师团队现在已经坚持了大约30个小时。
我们编写了一个NCO模块（生成一个正弦波），所有它都是一个周期的四分之一存储在一个块中，假设600个样本是四分之一。
比数学是增加/减少块rom以产生一个很好的正弦波。
几个月前我们就做了这个逻辑。
它一直在努力。
现在我们添加了使用正弦波表输出但不影响正弦生成的逻辑。
现在，正弦地址随机增加+30或+60（从逻辑分析仪中检索到）。
因此，我们回到较早的逻辑负载，并开始一次添加少量逻辑，直到它中断，因为我们无法通过模拟找到问题。
我们添加逻辑并最终打破，我们回到之前的逻辑负载，然后慢慢添加更小的数量，最终我们添加所有逻辑，它不再中断。
因此，空白区域中不同位置的相同代码将导致我们的正弦生成失败。
我看到一些令我害怕的事情：
我们的工程师在模块中使用了所有不同的库
库IEEE;使用IEEE.STD_LOGIC_1164.ALL;使用IEEE.STD_LOGIC_UNSIGNED.ALL;
使用work.utilities.ALL;
使用IEEE.NUMERIC_STD.ALL;
我有一些使用这些库的模块：
库IEEE;使用IEEE.STD_LOGIC_1164.ALL;使用IEEE.STD_LOGIC_SIGNED.ALL;
使用work.utilities.ALL;
以及使用这些库的一些模块：
库IEEE;使用IEEE.STD_LOGIC_1164.ALL;使用work.utilities.ALL;
使用IEEE.STD_LOGIC_ARITH.ALL;使用IEEE.STD_LOGIC_UNSIGNED.ALL;
我们使用不同的标准在不同的模块中进行+和 - 。
工具14.5 Ise项目导航器是否会引起混淆并开始执行此类行为？
该项目是15000行VHDL，几乎严格在std_logic / std_logic_vector中。
我应该将所有内容更改为Numeric并执行unsigned / signed多数，并仅将其转换为std_logic_vector以获取ip内核吗？
我也在使用VHDL-93标准，因为这是我公司一直以来的方式。
标准可能是我的问题的原因吗？
顺便说一句，我的逻辑编译并传递时间。



以下为原文

Thanks G,
 
You reply to over 50% of my questions :).
 
I am having very weird issues, that my engineer team has been stuck on for about 30 hours now.  
 
We have written an NCO module (Generates a sine wave) and all it is quarter of a cycle is stored in a block rom lets say 600 samples is a quarter.  Than math is made to increment/decrement the the block rom to produce a nice sine wave.  
 
We made this logic months ago.  It has been working.  Now we have added logic that uses the output of the sine wave table but doesn't affect the generation of the sine.  
 
Now the Sine address are incrementing by +30 or +60 at random times (Retrieved this from logic analyzer).  
 
So we go back to an earlier logic load and start adding in small amounts of logic at a time till it breaks, because we couldn't find the issue via simulation.   
 
We add logic and eventually it breaks,  We go back to the previous logic load that worked and slowly add even smaller amounts and eventually we add all the logic and it no longer breaks.
 
So same code in different spots in the white space will cause our sine generation to fail.
 
I see some things that scare me:
 
1.  Our engineers used all different libraries in modules
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.utilities.ALL;  
use IEEE.NUMERIC_STD.ALL;
 
 
I have some modules using these libraries:
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;
use work.utilities.ALL;
 
And some modules using these libraries:
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.utilities.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
We do + and - in different modules using different Standards.  Will the tools 14.5 Ise project navigator be caused confusion and start doing this type of behavior?
 
The project is 15000 lines of VHDL and almost strictly in std_logic/std_logic_vector.  Should I be changing everything to Numeric and doing unsigned/signed majority and only cast it to std_logic_vector for ip cores?
 
I am also using  VHDL-93 Standard, because that is the way my company has always done.  Could the standard be the cause of my issues?  
 
Btw my logic compiles and passes timing.

受到警告

None


以下为原文

As of right now we are using default settings on the project.
 
I am not really an expert in the tcl commands yet or have even begun to use them.
 
If I use the Project navigator GUI,   
 
my -timing is unchecked
 
my -ol  is greyed out  High
-xe is greyed out at none
 
-t is greyed out at 1
 
 
Should I check -timing and put extra effort and change the 
 
Starting cost table to 2, then 3.  See if problems still exist.
 
I have tried another thing:
 
My system runs off a 25 Mhz SSO oscilattor.
 
I have 3 dcms:
 
DCM_SP_inst : DCM_SP
generic map (
CLKDV_DIVIDE => 10.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
-- 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
CLKFX_DIVIDE => 1, -- Can be any interger from 1 to 32
CLKFX_MULTIPLY => 5, -- Can be any integer from 1 to 32
CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature
CLKIN_PERIOD => 40.0, -- Specify period of input clock
CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift of "NONE", "FIXED" or "VARIABLE"
CLK_FEEDBACK => "1X", -- Specify clock feedback of "NONE", "1X" or "2X"
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- "SOURCE_SYNCHRONOUS", "SYSTEM_SYNCHRONOUS" or
-- an integer from 0 to 15
DLL_FREQUENCY_MODE => "LOW", -- "HIGH" or "LOW" frequency mode for DLL
DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 255
STARTUP_WAIT => TRUE) -- Delay configuration DONE until DCM_SP LOCK, TRUE/FALSE
port map (
CLK0 => clk_25Mhz, -- 0 degree DCM CLK ouptput
CLK180 => open, -- 180 degree DCM CLK output
CLK270 => open, -- 270 degree DCM CLK output
CLK2X => open, -- 2X DCM CLK output
CLK2X180 => open, -- 2X, 180 degree DCM CLK out
CLK90 => open, -- 90 degree DCM CLK output
CLKDV => open,--clkdiv_15, -- Divided DCM CLK out (CLKDV_DIVIDE)
CLKFX => clk125MHz, -- DCM CLK synthesis out (M/D)
CLKFX180 => open, -- 180 degree CLK synthesis out
LOCKED => clk_lock, -- DCM LOCK status output
PSDONE => open, -- Dynamic phase adjust done output
STATUS => open, -- 8-bit DCM status bits output
CLKFB => clk_25Mhz, -- DCM clock feedback
CLKIN => clk,--clk_25Mhz, -- Clock input (from IBUFG, BUFG or DCM)
PSCLK => open, -- Dynamic phase adjust clock input
PSEN => open, -- Dynamic phase adjust enable input
PSINCDEC => open, -- Dynamic phase adjust increment/decrement
RST => '0' -- DCM asynchronous reset input
);
DCM_SP_inst2 : DCM_SP
generic map (
CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
-- 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
CLKFX_DIVIDE => 1, -- Can be any interger from 1 to 32
CLKFX_MULTIPLY => 2, -- Can be any integer from 1 to 32
CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature
CLKIN_PERIOD => 8.0, -- Specify period of input clock
CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift of "NONE", "FIXED" or "VARIABLE"
CLK_FEEDBACK => "2X", -- Specify clock feedback of "NONE", "1X" or "2X"
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- "SOURCE_SYNCHRONOUS", "SYSTEM_SYNCHRONOUS" or
-- an integer from 0 to 15
DLL_FREQUENCY_MODE => "LOW", -- "HIGH" or "LOW" frequency mode for DLL
DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 255
STARTUP_WAIT => TRUE) -- Delay configuration DONE until DCM_SP LOCK, TRUE/FALSE
port map (
CLK0 => open, -- 0 degree DCM CLK ouptput
CLK180 => open, -- 180 degree DCM CLK output
CLK270 => open, -- 270 degree DCM CLK output
CLK2X => clk2x, -- 2X DCM CLK output
CLK2X180 => clk180, -- 2X, 180 degree DCM CLK out
CLK90 => open, -- 90 degree DCM CLK output
CLKDV => open, -- Divided DCM CLK out (CLKDV_DIVIDE)
CLKFX => open, -- DCM CLK synthesis out (M/D)
CLKFX180 => open, -- 180 degree CLK synthesis out
LOCKED => open, -- DCM LOCK status output
PSDONE => open, -- Dynamic phase adjust done output
STATUS => open, -- 8-bit DCM status bits output
CLKFB => clk2x, -- DCM clock feedback
CLKIN => clk125MHz, -- Clock input (from IBUFG, BUFG or DCM)
PSCLK => open, -- Dynamic phase adjust clock input
PSEN => open, -- Dynamic phase adjust enable input
PSINCDEC => open, -- Dynamic phase adjust increment/decrement
RST => '0' -- DCM asynchronous reset input
);

DCM_SP_inst3 : DCM_SP
generic map (
CLKDV_DIVIDE => 10.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
-- 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
CLKFX_DIVIDE => 1, -- Can be any interger from 1 to 32
CLKFX_MULTIPLY => 2, -- Can be any integer from 1 to 32
CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature
CLKIN_PERIOD => 40.0, -- Specify period of input clock
CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift of "NONE", "FIXED" or "VARIABLE"
CLK_FEEDBACK => "1X", -- Specify clock feedback of "NONE", "1X" or "2X"
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- "SOURCE_SYNCHRONOUS", "SYSTEM_SYNCHRONOUS" or
-- an integer from 0 to 15
DLL_FREQUENCY_MODE => "LOW", -- "HIGH" or "LOW" frequency mode for DLL
DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 255
STARTUP_WAIT => TRUE) -- Delay configuration DONE until DCM_SP LOCK, TRUE/FALSE
port map (
CLK0 => clk_fb, -- 0 degree DCM CLK ouptput
CLK180 => open, -- 180 degree DCM CLK output
CLK270 => open, -- 270 degree DCM CLK output
CLK2X => open, -- 2X DCM CLK output
CLK2X180 => open, -- 2X, 180 degree DCM CLK out
CLK90 => open, -- 90 degree DCM CLK output
CLKDV => clk_dv, -- Divided DCM CLK out (CLKDV_DIVIDE)
CLKFX => open, -- DCM CLK synthesis out (M/D)
CLKFX180 => open, -- 180 degree CLK synthesis out
LOCKED => open, -- DCM LOCK status output
PSDONE => open, -- Dynamic phase adjust done output
STATUS => open, -- 8-bit DCM status bits output
CLKFB => clk_fb, -- DCM clock feedback
CLKIN => clk_25Mhz, -- Clock input (from IBUFG, BUFG or DCM)
PSCLK => open, -- Dynamic phase adjust clock input
PSEN => open, -- Dynamic phase adjust enable input
PSINCDEC => open, -- Dynamic phase adjust increment/decrement
RST => '0' -- DCM asynchronous reset input
);
 
Which creates  a clk_dv divided by 10 (2.5 MHz,  a clk 5X (125 MHz) , and a Clk2x  the Clk 5X (250 Mhz), and Clk2x180 of clk 5X (250 Mhz 180)  (THIS LAST CLOCK used for ODDR)
 
I tried replacing the external oscillator with a 20 Mhz oscillator and the logic still fails the same way.
 

I do admit I am inexperienced when it comes to timing constraints.  I have been doing this work for 3 years now and I have started from scratch with no senior engineer to guide me along.  
 
I went through the timing constraints guides and came up with these constraints:
 
NET "clk" TNM_NET = clk_25Mh;
TIMESPEC TS_clk_25Mhz = PERIOD "clk_25Mh" 40 ns HIGH 50 %; 
 
NET "fpga_bus<4>" TNM_NET = fpga_bus<4>;
TIMESPEC TS_fpga_bus_4_ = PERIOD "fpga_bus<4>" 40 ns HIGH 50%;
INST "fpga_bus<1>" TNM = FPGA_BUS_INPUT;
INST "fpga_bus<2>" TNM = FPGA_BUS_INPUT;
INST "fpga_bus<3>" TNM = FPGA_BUS_INPUT;
INST "fpga_bus<4>" TNM = FPGA_BUS_INPUT;
TIMEGRP "FPGA_BUS_INPUT" OFFSET = IN 10 ns VALID 20 ns BEFORE "fpga_bus<4>" FALLING;
NET "fpga_bus<0>" OFFSET = OUT 9 ns AFTER "clk";
 
And than I assume that the DCM makes the other clock constraints.  I am not sure what other constraints I would need.
 
Thank you so much for your time, it is very hard sometimes to figure out a problem if there is no one to give you help or ideas.