是的，我已经评论过“rising_edge（F_Clk）”部分它没有，但它包含在代码中对不起。
如果你在代码中看到了错误 - 或者没有意义的东西 - 你是否能够改变它？
我的目标是捕获在D_Clk的上升沿和下降沿发送的LVDS数据，因此我无法添加“if（D_Clk'event和D_clk ='1'）或类似的那样。
在时钟的上升沿采样LVDS数据的寄存器与在相同（不同）时钟的下降沿采样LVDS数据的寄存器是分开的。
你能理解这个吗？
如果你可以创建一个新的寄存器类型来捕获两个时钟边沿的数据，你完成了什么？
您从DDR数据开始，您将获得DDR数据。
你能理解这个吗？
所以'奇数'数据被捕获在'posedge'上的时钟寄存器中，'even'数据被捕获在'negedge'上的时钟寄存器中。
您可以使用简单的HDL代码（可能使用结构逻辑）来完成此操作，或者如果您希望在IO块中完成1：2解复用，则可以实例化IDDR原语。
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
搜索论坛（并搜索网页）以寻找类似的主题。
不要在多个论坛上发布相同的问题。
不要在别人的主题上发布新主题或问题，开始新的主题！5。
学生：复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。
提供有用的详细信息（请与网页，数据表链接）.7。
您的代码中的评论不需要支付额外费用。
我没有支付论坛帖子的费用。
如果我写一篇好文章，那么我一无所获。
在原帖中查看解决方案
以上来自于谷歌翻译
以下为原文
Yeah, I have commented that "rising_edge(F_Clk) " part it does not , however it is included in the code sorry about that.
If you see something wrong -- or something which does not make sense -- in the code, are you not able to change it?
My aim is to capture the LVDS data sent in both rising and falling edges of that D_Clk so I could not add "if (D_Clk'event and D_clk='1') or sth. like that.
The register which samples LVDS data on the rising edge of the clock is separate from the register which samples LVDS data on the falling edge of the same (
not different) clock. Does this make sense to you?
If you could create a new register type which captures data on both clock edges, what have you accomplished? You started with DDR data and you are left with DDR data. Does this make sense to you?
So 'odd' data are captured in registers clocked on 'posedge' and 'even' data are captured in registers clocked on 'negedge'.
You can accomplish this with simple HDL code (probably using fabric logic), or you can instantiate the IDDR primitive if you want the 1:2 de-multiplexing accomplished in the IO blocks.
-- Bob Elkind
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369
Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.View solution in original post
是的，我已经评论过“rising_edge（F_Clk）”部分它没有，但它包含在代码中对不起。
如果你在代码中看到了错误 - 或者没有意义的东西 - 你是否能够改变它？
我的目标是捕获在D_Clk的上升沿和下降沿发送的LVDS数据，因此我无法添加“if（D_Clk'event和D_clk ='1'）或类似的那样。
在时钟的上升沿采样LVDS数据的寄存器与在相同（不同）时钟的下降沿采样LVDS数据的寄存器是分开的。
你能理解这个吗？
如果你可以创建一个新的寄存器类型来捕获两个时钟边沿的数据，你完成了什么？
您从DDR数据开始，您将获得DDR数据。
你能理解这个吗？
所以'奇数'数据被捕获在'posedge'上的时钟寄存器中，'even'数据被捕获在'negedge'上的时钟寄存器中。
您可以使用简单的HDL代码（可能使用结构逻辑）来完成此操作，或者如果您希望在IO块中完成1：2解复用，则可以实例化IDDR原语。
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
搜索论坛（并搜索网页）以寻找类似的主题。
不要在多个论坛上发布相同的问题。
不要在别人的主题上发布新主题或问题，开始新的主题！5。
学生：复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。
提供有用的详细信息（请与网页，数据表链接）.7。
您的代码中的评论不需要支付额外费用。
我没有支付论坛帖子的费用。
如果我写一篇好文章，那么我一无所获。
在原帖中查看解决方案
以上来自于谷歌翻译
以下为原文
Yeah, I have commented that "rising_edge(F_Clk) " part it does not , however it is included in the code sorry about that.
If you see something wrong -- or something which does not make sense -- in the code, are you not able to change it?
My aim is to capture the LVDS data sent in both rising and falling edges of that D_Clk so I could not add "if (D_Clk'event and D_clk='1') or sth. like that.
The register which samples LVDS data on the rising edge of the clock is separate from the register which samples LVDS data on the falling edge of the same (
not different) clock. Does this make sense to you?
If you could create a new register type which captures data on both clock edges, what have you accomplished? You started with DDR data and you are left with DDR data. Does this make sense to you?
So 'odd' data are captured in registers clocked on 'posedge' and 'even' data are captured in registers clocked on 'negedge'.
You can accomplish this with simple HDL code (probably using fabric logic), or you can instantiate the IDDR primitive if you want the 1:2 de-multiplexing accomplished in the IO blocks.
-- Bob Elkind
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369
Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.View solution in original post
举报
