如何为设计计算IDELAY_VALUE的值？

我在sp601板上使用tri-ethernet-mac示例。
gmii接收器接口使用IODELAY2原语来延迟接收器侧的输入信号。
vhdl代码提到应该根据设计在ucf中更改IDELAY_VALUE。
我阅读了i / o延迟概述，但无法了解如何为设计计算IDELAY_VALUE的值？
根据ug 138的193页，所需的最小设置时间为2ns，保持时间为0 ns。
如果有人能提供帮助，我将不胜

以上来自于谷歌翻译

以下为原文

I am using tri-ethernet-mac example for sp601 board.

The gmii receiver interface uses IODELAY2 primitive to delay the input signal on the receiver side.

The vhdl code mentions that IDELAY_VALUE should be changed in ucf as per the design.

I read the i/o delay overview but could not get an idea on how to calculate the value of IDELAY_VALUE for the design?

The minimum set up time required is 2ns and hold time 0 ns as per 193 page of ug 138.

Would appreciate if someone can help.

马杰

2019-5-28 06:50:08

你好，
a）查看帖子http://forums.xilinx.com/t5/Spartan-Family-FPGAs/iodelay2-min-max-delay/td-p/116418
b）当iodelay用于固定模式时，跟踪报告将为您提供最小/最大延迟
希望这可以帮助，
菲利普。

以上来自于谷歌翻译

以下为原文

Hello,

a) have a look to the post http://forums.xilinx.com/t5/Spartan-Family-FPGAs/iodelay2-min-max-delay/td-p/116418

b) when iodelay is used in fixed mode, the trace report will give you the min/max delay

Hope this helps,

Philippe.