首先，您没有提及您的时钟频率，但随着频率上升，DCM将占空比调整为50％的能力变得不那么准确。
这是由于用于生成DCM的输出波形的固定延迟元件。
DCM不是Spartan 3中的锁相环。
无论如何，我发现FPGA不太可能比你在Spartan 3中的50.3％占空比做得更好。
在较高频率下，占空比测量受信号阈值电平的影响很大，因为信号花费的时钟周期的较大部分从低电平变为高电平或从高电平变为低电平。
将时钟驱动到输出引脚也可以改变占空比
由于低到高与高到低传播延迟的差异。
您可以通过使用差分IO标准（如LVDS）来最小化此类问题。
通过在内部全局时钟信号的两个边沿上使用的DDR IOB输出寄存器，可以最佳地再现输出引脚的内部时钟信号。
该方法用于所有DDR存储器设计，用于驱动外部SDRAM芯片的时钟。
关于时钟信号完整性有很多应用笔记，包括占空比和周期到周期抖动。
这些都表明FPGA不是用作时钟源的理想元件。
DCM不会减少周期抖动，正如我所提到的，它们调整占空比的能力受到延迟链的离散性质的限制。
您还没有说过为什么50.3％的占空比在您的应用中不够好，但我建议您为生成时钟而不是使用FPGA寻找专用的PLL芯片解决方案。
问候，
的Gabor
- Gabor
以上来自于谷歌翻译
以下为原文
First of all, you don't mention your clock frequency, but as the frequency goes up the ability of the DCM to adjust the duty cycle to 50% becomes less accurate. This is due to the fixed delay elements used to generate the output waveform of the DCM. The DCM is not a phase-locked loop in Spartan 3.
In any case I find it unlikely that an FPGA can do better than the 50.3% duty cycle that you are putting into the Spartan 3.
At higher frequencies, the duty cycle measurement is affected greatly by the threshold level of the signal, since the signal is spending a larger portion of the clock cycle transitioning from low to high or high to low. Also driving a clock to an output pin can change the duty cycle justdue to differences in the low-to-high vs high-to-low propagation delays. You can minimize this sort of problem by using a differential IO standard like LVDS. Your best reproduction of an internal clock signal to an output pin will come by using the DDR IOB output register clocked on both edges of the internal global clock signal. This method is used in all of the DDR memory designs for driving the clocks to the external SDRAM chips.
There are a lot of application notes about clock signal integrity including duty cycle and cycle to cycle jitter. These all point to the fact that an FPGA is not an ideal component to use as a clock source. DCM's will not reduce cycle jitter, and as I mentioned, their ability to adjust the duty cycle is limited by the discrete nature of their delay chains. You haven't said why 50.3% duty cycle is not good enough in your application, but I would suggest looking for a dedicated PLL chip solution for your clock generation rather than using an FPGA.
Regards,
Gabor
-- Gabor
首先，您没有提及您的时钟频率，但随着频率上升，DCM将占空比调整为50％的能力变得不那么准确。
这是由于用于生成DCM的输出波形的固定延迟元件。
DCM不是Spartan 3中的锁相环。
无论如何，我发现FPGA不太可能比你在Spartan 3中的50.3％占空比做得更好。
在较高频率下，占空比测量受信号阈值电平的影响很大，因为信号花费的时钟周期的较大部分从低电平变为高电平或从高电平变为低电平。
将时钟驱动到输出引脚也可以改变占空比
由于低到高与高到低传播延迟的差异。
您可以通过使用差分IO标准（如LVDS）来最小化此类问题。
通过在内部全局时钟信号的两个边沿上使用的DDR IOB输出寄存器，可以最佳地再现输出引脚的内部时钟信号。
该方法用于所有DDR存储器设计，用于驱动外部SDRAM芯片的时钟。
关于时钟信号完整性有很多应用笔记，包括占空比和周期到周期抖动。
这些都表明FPGA不是用作时钟源的理想元件。
DCM不会减少周期抖动，正如我所提到的，它们调整占空比的能力受到延迟链的离散性质的限制。
您还没有说过为什么50.3％的占空比在您的应用中不够好，但我建议您为生成时钟而不是使用FPGA寻找专用的PLL芯片解决方案。
问候，
的Gabor
- Gabor
以上来自于谷歌翻译
以下为原文
First of all, you don't mention your clock frequency, but as the frequency goes up the ability of the DCM to adjust the duty cycle to 50% becomes less accurate. This is due to the fixed delay elements used to generate the output waveform of the DCM. The DCM is not a phase-locked loop in Spartan 3.
In any case I find it unlikely that an FPGA can do better than the 50.3% duty cycle that you are putting into the Spartan 3.
At higher frequencies, the duty cycle measurement is affected greatly by the threshold level of the signal, since the signal is spending a larger portion of the clock cycle transitioning from low to high or high to low. Also driving a clock to an output pin can change the duty cycle justdue to differences in the low-to-high vs high-to-low propagation delays. You can minimize this sort of problem by using a differential IO standard like LVDS. Your best reproduction of an internal clock signal to an output pin will come by using the DDR IOB output register clocked on both edges of the internal global clock signal. This method is used in all of the DDR memory designs for driving the clocks to the external SDRAM chips.
There are a lot of application notes about clock signal integrity including duty cycle and cycle to cycle jitter. These all point to the fact that an FPGA is not an ideal component to use as a clock source. DCM's will not reduce cycle jitter, and as I mentioned, their ability to adjust the duty cycle is limited by the discrete nature of their delay chains. You haven't said why 50.3% duty cycle is not good enough in your application, but I would suggest looking for a dedicated PLL chip solution for your clock generation rather than using an FPGA.
Regards,
Gabor
-- Gabor
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