赛灵思
直播中

李昕萌

7年用户 245经验值
私信 关注
[问答]

怎么从ISE 14.1 SmartXplorer运行PAR


我有这个大设计,我已经在FPGA(virtex 6设备)上实现了。
其中一个设计时钟(clk xyz)需要运行@ 125MHz。
然而,实现该设计仅提供约88MHz。
我尽可能地限制了设计(无论我有什么关于虚假路径的信息)。
所以我使用SmartXplorer并以下列方式运行它 -
1)时序改进策略 -  12次运行 - 这将迭代各种MAP选项以获得最佳性能
- 这为时钟xyz提供了97MHz的最佳情况(使用MapLogicOpt策略)
2)仅在成本表上迭代 -  12次运行 - 尝试不同的PAR。
- 这为时钟xyz提供了104MHz的最佳情况
现在,当我在FPGA上尝试位文件时,104MHz位文件没有按预期工作。
但是97MHz位文件确实有效。
我的问题是 - 这可能是一个“侥幸”,即较慢的位文件正在工作,但不是一个时间更好的时间?
可能是它背后的原因,我在哪里可以看到它?
我可以在两次运行之间比较的任何文件?
将运行smartxplorer与成本表上的更多迭代有助于改善clk xys的时间?
如果我想从最好的smartxplorer运行其他实现运行的PAR,那么最好的方法是什么?
现在,我使用planahead并锁定BRAM实例(xilinx文档说像DSP,BRAMS,arith单元等锁定原语),这给了我ucf文件中新的loc约束。
然后,我在其他xilinx实现运行中使用这些约束来尝试在某种程度上保留PAR。
这是保留PAR的方法还是有更好的方法可以做到这一点?
我可以尝试使用smartxplorer来改善时序并使位文件更加可靠吗?
所有上述内容都在xilinx 14.1 ISE中。

以上来自于谷歌翻译


以下为原文

hi,

i have this BIG design which i have implemented on the fpga (a virtex 6 device).

one of the clocks of the design (clk xyz) needs to run @ 125MHz.  however implementing the design only gives about 88MHz. I have constrained the design the best I can (with whatever info I had regarding false paths etc.).

so i used SmartXplorer and ran it in the following manner -
1) timing improvement strategy - 12 runs - this would iterate through the various MAP options for best performance
-this gave a best case of 97MHz for clock xyz (using the MapLogicOpt strategy)
2) iterate only on cost table - 12 runs - to try different PAR.
-this gave a best case of 104MHz for clock xyz

Now when I tried the bit files on the FPGA, the 104MHz bit file did not work as expected. However the 97MHz bit file did work.

My question is - could this be a "fluke" i.e. a slower bit file is working but not the one with a slighlty better timing?
what could be the reasons behind it and where can i look to zero in on it? any files that i can compare between the two runs?

will running smartxplorer with more iterations on the cost table help improve the timing of clk xys?

If I want  to retian the PAR from the best smartxplorer run for some other implementation run, what is the best way to do that?
for now, i use planahead and lock the BRAM instances (xilinx document says lock primitives like DSP, BRAMS, arith units etc.), which gives me new loc constraints in the ucf file. I then use these constraints in other xilinx implementation runs to try and retain the PAR to some extent. is this the way to retain PAR or is there some better method to do so?

any other things I can try with smartxplorer to improve timing and make the bit file more relaible?

all of the above in xilinx 14.1 ISE.

回帖(7)

赵雪培

2019-4-8 08:27:57
嗨,
您似乎已经做了正确的事情来缩短最佳频率的时间。
阅读Pg 142,为smartxplorer选择最佳策略-http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_1/devref.pdf
浏览这些指南,看看你是否能找到新的东西。
http://www.xilinx.com/itp/xilinx10/isehelp/ise_c_using_smart_xplorer.htm
http://www.xilinx.com/support/documentation/sw_manuals/xilinx13_1/ug689.pdf
谢谢,AnirudhPS:请将此标记作为答案,以防它有助于解决您的问题。如果帖子引导您找到解决方案,请给予赞誉。

以上来自于谷歌翻译


以下为原文

Hi,
 
You seem to have done the right things for closing the timing for best possible frequency. 
 
read through Pg 142 on selecting the best strategy for smartxplorer- http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_1/devref.pdf
 
 
Skim through these guide and see if you can find something new.
 
http://www.xilinx.com/itp/xilinx10/isehelp/ise_c_using_smart_xplorer.htm
http://www.xilinx.com/support/documentation/sw_manuals/xilinx13_1/ug689.pdf
 
Thanks,
Anirudh

PS: Please MARK this as an answer in case it helped resolve your query.Give kudos in case the post guided you to a solution.
举报

赵雪培

2019-4-8 08:35:27
嗨,
在任何情况下,您可能还需要手动查看代码,看看是否有一些简单的路径可以为计时而烦恼,或者您是否可以更改编码以便可以删除数据路径中的某些寄存器,
改善时间或类似的东西
谢谢,AnirudhPS:请将此标记作为答案,以防它有助于解决您的问题。如果帖子引导您找到解决方案,请给予赞誉。

以上来自于谷歌翻译


以下为原文

Hi,
 
In any case, you may also have to manually have a look at the code to see if there are some simple paths which can be ingnored for timing or if you can change the coding so that certain registers in the data path can be removed which can improve the timing or something simiilar
Thanks,
Anirudh

PS: Please MARK this as an answer in case it helped resolve your query.Give kudos in case the post guided you to a solution.
举报

刘丽艳

2019-4-8 08:53:48
anirudh,
我已经浏览了这些文档,我已经阅读过它们了。
这就是让我走到这一步的原因。
我需要知道的是 - 哪些因素可能导致比较慢的位文件或来自第二个最佳策略的位文件比一个更好的策略或位文件的位文件表现更好,这会在同一个时钟总线上产生低容量,如问题
我问

以上来自于谷歌翻译


以下为原文

anirudh,
 
i've already skimmed through these docs and i have read them. that is what got me this far.
 
what i need to know is - what factors could lead to a slower bit file or a bit file from the 2nd best strategy performing better than a bitfile from a better strategy or bitfile which gives a lowe slack on the same clock bus, like the questions i asked
举报

刘丽艳

2019-4-8 09:02:09

我不能改变代码,因为它是一个IP。
所以我必须依靠工具/ smartxplorer来获得最好的时间。
至于查看代码并手动查找各种错误路径等,该信息驻留在设计器上......它是一个IP。
所以我们不能确定哪条路可以忽略。

以上来自于谷歌翻译


以下为原文

hi,
 
i cant change the code as it's an IP. so i have to rely on tools/smartxplorer for the best possible timining. as for looking at the code and manually and figuring out various false paths etc., that information resides with designer .. and it's an IP. so we can't say for sure which path can be ignored or not.
举报

更多回帖

发帖
×
20
完善资料,
赚取积分