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[问答]

在布局和路线之后怎么更改BRAM的内容

你好,
我在FPGA(ISE14)中有一个部分重配置设计,它包含一个由coregen生成的BRAM存储器块。
在整个设计布线后,我需要能够改变这些存储器的内容。
我知道data2mem程序可以完成类似的任务。
但是为了使用data2mem,我需要知道哪个BLOCKRAM对应于整个存储器块中的哪个地址。
例如,当每行存储8位数时,我有6000行的内存,而coregen使用4个BlockRAM来实现这样的内存。
现在,在布局和布线之后,我有一个包含行数和要存储在内存中的数字的文件(可能是coe),我需要将这些值放入右侧blockram,而不再运行地点和路径。
有没有办法如何生成正确的bmm文件并将其与比特流连接?
谢谢你的每一个指针。
一月

以上来自于谷歌翻译


以下为原文

Hello,

I have a Partial reconfiguration design in the FPGA (ISE14) that contain a block of BRAM memories generated by the coregen. I need to be able to change the content of these memories after the whole design is routed.

I know that similar task can be accomplished by the data2mem program. But to use data2mem I need to know which address in which BLOCKRAM corresponds to which address in the whole block of memories. For example, I have memory that has 6000 lines when every line store 8bit number and coregen uses 4 BlockRAM to implement such memory. Now, after the place and route, I have the file containing the number of line and the number to be stored in the memory (may be in coe) and I need to place these values into right blockram without running the place and route again.

Is there any way how to generate correct bmm file and connect it with the bitstream? Thanks you for every pointers.
Jan

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李富才

2018-10-16 06:47:21
由于地址引脚通常被换掉以实现可路由性,因此RAM内容被加扰,这一点变得复杂。
我不知道有人这样成功。

以上来自于谷歌翻译


以下为原文

This is all complicated by the fact that the address pins usually get swapped around for routability and so the RAM contents are scrambled. I'm not aware of anyone doing this successfully.
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李大帅

2018-10-16 06:59:27
嗨,
实际上我认为XPS / SDK在生成比特流后允许你下载微博的程序时会有类似的想法。
我的意思是在XPS / SDK中,我可以生成包含一个或多个微光泽处理器的硬件设计,并为此设计生成比特流。
之后我可以将设计导出到SDK中并编写用于microblaze的程序(例如bootloader或简单的内存测试)然后我可以在FPGA中运行该程序而无需重新路由。
是否有可能采用XPS / SDK方法进行自己的设计?
谢谢

以上来自于谷歌翻译


以下为原文

Hi,
 
Actually I was under the impression that the XPS/SDK does similar think when it allows you to download the program for the microblaze after the bitstream was generated. I mean that in the XPS/SDK, I can generate HW design containing one or more microblaze processors and generate bitstream for this design. After that I may export the design into the SDK and write the program for microblaze (for example bootloader, or simple memory test) and then I can run this program in the FPGA without the need for rerouting.
 
Is there any possibility how to adopt the XPS/SDK approach to my own design?
 
Thanks
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