LCD显示问题

功能：控制1602液晶屏，显示两行字符，第一行内容:”NEW: 123.456MHz”,第二行内容:”OLD:789.345MHz”，过1S后将第一行和第二行的内容变换显示。

module test(clk, rs, rw, en,dat,LCD_N,LCD_P);

input clk;

output [7:0] dat;

output rs,rw,en,LCD_N,LCD_P;

//tri en;

reg e;

reg [7:0] dat;

reg rs;

reg [15:0] counter;

reg [7:0] current,next;

reg clkr;

reg [1:0] cnt=2'b00;

reg flag,flag_reg;

reg [8:0] cnt_clkr=9'b0;

wire [7:0] data0;//assign fu zhi bi xu shi wire xing

wire [7:0] data1;

wire [7:0] data2;

wire [7:0] data3;

wire [7:0] data4;

wire [7:0] data5;

wire [7:0] data6;

wire [7:0] data7;

wire [7:0] data8;

wire [7:0] data9;

wire [7:0] data10;

wire [7:0] data11;

wire [7:0] data12;

wire [7:0] data13;

wire [7:0] data14;

wire [7:0] data15;

wire [7:0] data16;

wire [7:0] data17;

wire [7:0] data18;

wire [7:0] data19;

wire [7:0] data20;

wire [7:0] data21;

wire [7:0] data22;

wire [7:0] data23;

wire [7:0] data24;

wire [7:0] data25;

wire [7:0] data26;

wire [7:0] data27;

parameter set0=8'h00;

parameter set1=8'h01;

parameter set2=8'h02;

parameter set3=8'h03;

parameter set4=8'h04;

parameter set5=8'h05;

parameter dat0=8'h06;

parameter dat1=8'h07;

parameter dat2=8'h08;

parameter dat3=8'h09;

parameter dat4=8'h0A;

parameter dat5=8'h0B;

parameter dat6=8'h0C;

parameter dat7=8'h0D;

parameter dat8=8'h0E;

parameter dat9=8'h0F;

parameter dat10=8'h10;

parameter dat11=8'h11;

parameter dat12=8'h12;

parameter dat13=8'h13;

parameter dat14=8'h14;

parameter dat15=8'h15;

parameter dat16=8'h16;

parameter dat17=8'h17;

parameter dat18=8'h18;

parameter dat19=8'h19;

parameter dat20=8'h1A;

parameter dat21=8'h1B;

parameter dat22=8'h1C;

parameter dat23=8'h1D;

parameter dat24=8'h1E;

parameter dat25=8'h1F;

parameter dat26=8'h20;

parameter dat27=8'h2A;

parameter nul=8'hFF;

assign LCD_N=0;

assign LCD_P=1;

assign data0 = flag? "O" : "N";

assign data1 = flag? "L" : "E";

assign data2 = flag? "D" : "W";

assign data3 = flag? ":" : ":";

assign data4 = flag? "7" : "1";

assign data5 = flag? "8" : "2";

assign data6 = flag? "9" : "3";

assign data7 = flag? "." : ".";

assign data8 = flag? "3" : "4";

assign data9 = flag? "4" : "5";

assign data10 = flag? "5" : "6";

assign data11 = flag? "M" : "M";

assign data12 = flag? "H" : "H";

assign data13 = flag? "Z" : "Z";

assign data14 = flag? "N" : "O";

assign data15 = flag? "E" : "L";

assign data16 = flag? "W" : "D";

assign data17 = flag? ":" : ":";

assign data18 = flag? "1" : "7";

assign data19 = flag? "2" : "8";

assign data20 = flag? "3" : "9";

assign data21 = flag? "." : ".";

assign data22 = flag? "4" : "3";

assign data23 = flag? "5" : "4";

assign data24 = flag? "6" : "5";

assign data25 = flag? "M" : "M";

assign data26 = flag? "H" : "H";

assign data27 = flag? "Z" : "Z";

always @(posedge clk)

begin

counter<=counter+1;

if(counter==16'b1100001101001111)

clkr<=~clkr;
end
always @(posedge clkr)

begin

current=next;

case(current)


set0: begin rs<=0; dat<=8'h38; next<=set1; end

set1: begin rs<=0; dat<=8'h0C; next<=set2; end

set2: begin rs<=0; dat<=8'h06; next<=set3; end

set3: begin rs<=0; dat<=8'h01; next<=set4; end

set4: begin rs<=0; dat<=8'h80; next<=dat0; end



dat0: begin rs<=1; dat<=data0; next<=dat1; end

dat1: begin rs<=1; dat<=data1; next<=dat2; end

dat2: begin rs<=1; dat<=data2; next<=dat3; end

dat3: begin rs<=1; dat<=data3; next<=dat4; end

dat4: begin rs<=1; dat<=data4; next<=dat5; end

dat5: begin rs<=1; dat<=data5; next<=dat6; end

dat6: begin rs<=1; dat<=data6; next<=dat7; end

dat7: begin rs<=1; dat<=data7; next<=dat8; end

dat8: begin rs<=1; dat<=data8; next<=dat9; end

dat9: begin rs<=1; dat<=data9; next<=dat10; end

dat10: begin rs<=1; dat<=data10; next<=dat11; end

dat11: begin rs<=1; dat<=data11; next<=dat12; end

dat12: begin rs<=1; dat<=data12; next<=dat13; end

dat13: begin rs<=1; dat<=data13; next<=set5; end



set5: begin rs<=0;dat<=8'hC0;next<=dat14; end//设置第2行地址



dat14: begin rs<=1; dat<=data14; next<=dat15; end

dat15: begin rs<=1; dat<=data15; next<=dat16; end

dat16: begin rs<=1; dat<=data16; next<=dat17; end

dat17: begin rs<=1; dat<=data17; next<=dat18; end

dat18: begin rs<=1; dat<=data18; next<=dat19; end

dat19: begin rs<=1; dat<=data19; next<=dat20; end

dat20: begin rs<=1; dat<=data20; next<=dat21; end

dat21: begin rs<=1; dat<=data21; next<=dat22; end

dat22: begin rs<=1; dat<=data22; next<=dat23; end

dat23: begin rs<=1; dat<=data23; next<=dat24; end

dat24: begin rs<=1; dat<=data24; next<=dat25; end

dat25: begin rs<=1; dat<=data25; next<=dat26; end

dat26: begin rs<=1; dat<=data26; next<=dat27; end

dat27: begin rs<=1; dat<=data27; next<=set4; end

default: next<=set0;

endcase

end



always @(posedge clkr)

begin


if(cnt_clkr<=9'b111110100)

begin

cnt_clkr<=cnt_clkr+1;flag<=flag;

end

else

begin

flag<=~flag;cnt_clkr<=0;

end

end

assign en=clkr;

assign rw=0;

endmodule

效果：

显示别的程序正常，硬件没变化，第一次使用FPGA，指点一下

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