[问答]

关于FPGA 模拟SPI

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问答对人有帮助，内容完整，我也想知道答案 0 最近在学习SPI 从网上COPY了以下代码 /*********************************************************************************************** * SPI MASTER * January 2007 ***********************************************************************************************/ `timescale 10ns/1ns module SPI_Master ( miso, mosi, sclk, ss, data_bus, CS, addr, pro_clk, WR, RD); inout [7:0] data_bus; // 8 bit bidirectional data bus input pro_clk; // Host Processor clock input miso; // Master in slave out input [1:0] addr; // A1 and A0, lower bits of address bus input CS; // Chip Select input WR, RD; // Write and read enables output mosi; // Master out slave in output sclk; // SPI clock output [7:0] ss; // 8 slave select lines reg [7:0] shift_register; // Shift register reg [7:0] txdata; // Transmit buffer reg [7:0] rxdata; // Receive buffer reg [7:0] data_out; // Data output register reg [7:0] data_out_en; // Data output enable reg [7:0] control, status; // Control Register COntrols things like ss, CPOL, CPHA, clock divider // Status Register is a dummy register never used. reg [7:0] clk_divide; // Clock divide counter reg [3:0] count; // SPI word length counter reg sclk; reg slave_cs; // Slave cs flag reg mosi; // Master out slave in reg spi_word_send; // Will send a new spi word. wire [7:0] data_bus; wire [7:0] data_in = data_bus; wire spi_clk_gen; wire [2:0] divide_factor = control[2:0]; wire CPOL = control[3]; wire CPHA = control[4]; wire [7:0]ss; / Slave Select lines / assign ss[7] = ~( control[7] & control[6] & control[5] & (~slave_cs)); assign ss[6] = ~( control[7] & control[6] & ~control[5] & (~slave_cs)); assign ss[5] = ~( control[7] & ~control[6] & control[5] & (~slave_cs)); assign ss[4] = ~( control[7] & ~control[6] & ~control[5] & (~slave_cs)); assign ss[3] = ~(~control[7] & control[6] & control[5] & (~slave_cs)); assign ss[2] = ~(~control[7] & control[6] & ~control[5] & (~slave_cs)); assign ss[1] = ~(~control[7] & ~control[6] & control[5] & (~slave_cs)); assign ss[0] = ~(~control[7] & ~control[6] & ~control[5] & (~slave_cs)); / clock divide / assign spi_clk_gen = clk_divide[divide_factor]; / Clock Divider / always @ (negedge pro_clk) begin clk_divide = clk_divide + 1; end / Reading the miso line and shifting / always @ (posedge (sclk ^ (CPHA ^ CPOL)) or posedge spi_word_send) begin if (spi_word_send) begin shift_register[7:0] = txdata; end else begin shift_register = shift_register << 1; shift_register[0] <= miso; end end / Writing the mosi / always @ (negedge (sclk ^ (CPHA ^ CPOL)) or posedge spi_word_send) begin if (spi_word_send) begin mosi = txdata[7]; end else begin mosi = shift_register[7]; end end / Contolling the interrupt bit in the status bit / always @ (posedge slave_cs or posedge spi_word_send) begin if (spi_word_send) begin status[0] = 0; end else begin status = 8'h01; rxdata = shift_register; // updating read buffer end end / New SPI wrod starts when the transmit buffer is updated / always @ (posedge pro_clk) begin if (spi_word_send) begin slave_cs <= 0; end else if ((count == 8) & ~(sclk ^ CPOL)) begin slave_cs <= 1; end end / New Spi word is intiated when transmit buffer is updated / always @ (posedge pro_clk) begin if (CS & WR & addr[1] & ~addr[0]) begin spi_word_send <=1; end else begin spi_word_send <=0; end end / Generating the SPI clock / always @ (posedge spi_clk_gen) begin if (~slave_cs) begin sclk = ~sclk; end else if (~CPOL) begin sclk = 0; end else begin sclk = 1; end end / Counting SPI word length / always @ (posedge sclk or posedge slave_cs) begin if (slave_cs) begin count = 0; end else begin count = count + 1; end end / Reading, writing SPI registers / always @ (posedge pro_clk) begin if (CS) begin case (addr) 2'b00 : if (WR) control <= data_in; 2'b01 : if (RD) data_out <= status; // Void 2'b10 : if (WR) txdata <= data_in; 2'b11 : if (RD) data_out <= rxdata; endcase end end / Controlling the data out enable / always @ (RD or data_out) begin if (RD) data_out_en = data_out; else data_out_en = 8'bz; end assign data_bus = data_out_en; initial begin mosi = 0; //sclk = 0; control = 0; count = 0; slave_cs = 1; txdata = 0; rxdata = 0; clk_divide = 0; data_out = 0; end endmodule /******************************************* END ***************************************************************/ 复制代码* 可能是我对SPI理解得还不够深在FPGA作为master时像INPUT里面的addr WR RD OUTPUT 里面的 SS这些都是干什么的呢？ SPI总线不是最多四条就够了吗。求解释。最好是有应用的实例比如我想FPGA发送1HZ方波让单片机的LED闪动应该怎么接？ 0 已退回1积分
2015-8-14 12:26:30　　评论淘帖0 邀请回答您可以邀请以下用户，快速回答问题 × 刘英该类别下有 31 个回答。邀请回答 chenbingjy 该类别下有 27 个回答。邀请回答 yoonssica 该类别下有 22 个回答。邀请回答 houxiaoxiao 该类别下有 17 个回答。邀请回答小萃米该类别下有 16 个回答。邀请回答小工兵该类别下有 16 个回答。邀请回答 Elecfans管家该类别下有 15 个回答。邀请回答薄迪该类别下有 14 个回答。邀请回答我爱妖妖该类别下有 14 个回答。邀请回答言尽于此33 该类别下有 14 个回答。邀请回答 hxing 该类别下有 13 个回答。邀请回答那些年儿ing 该类别下有 13 个回答。邀请回答平漂流该类别下有 13 个回答。邀请回答 1653344032.827400 该类别下有 12 个回答。邀请回答小麦地该类别下有 12 个回答。邀请回答科比如我该类别下有 12 个回答。邀请回答倪love 该类别下有 12 个回答。邀请回答 xiekaboy 该类别下有 12 个回答。邀请回答黄月明该类别下有 11 个回答。邀请回答 tutu1583 该类别下有 11 个回答。邀请回答举报欧阳英杰相关推荐 • 在FPGA中模拟SPI接口要如何保证这个时序要求呀？ 2029 • FPGA与STM32模拟32位SPI通信常见的故障有哪些？ 1383 • 请教关于AD9122模拟输出基波频谱问题 1834 • 怎么从SPI闪存读取数据到FPGA 641 • 如何从PROM闪存和SPI闪存配置FPGA的PDF文件？ 1958 • 如何使用fpga上的SPI flash执行此操作？ 1801 • 无法看到FPGA的spi内核 1421 • 使用isim在不使用硬件的EDK平台上进行SPI ip核心仿真 1349 • 使用IO模拟SPI的话，硬件SPI还可以用吗？ 1380 • 如何使用stm32软件去模拟SPI通信呢 1353 1个回答

答案对人有帮助，有参考价值 0 先看看SPI的时序图，要不然通信协议都不会，不太好搞。。。

2015-8-25 16:01:22 评论举报 HelloWii