[NVIDIA]招聘 VLSI Physical Design Engineer(EDA Methodology）-Shanghai/Beijing

2015-3-3 11:02:12 2305

0 Hello All, 大家好，这边是NVIDIA HR Tracy, 我们目前在北京和上海有招聘VLSI Physical Design Engineer的岗位，具体职位描述如下，如果大家有意向，[url=mailto:可以发送简历到tracyw@nvidia.com]可以发送简历到tracyw@nvidia.com[/url]，收到简历我会及时与你们联系。 Senior/Physical Design Engineer--Description As senior role in physical design for NVIDIAGPU and Mobile chips. Participate in various aspects of physicaldesign, including full chip floor planning, power/clock distribution, timingoptimization, place & route, timing closure, power/signal integrity analysis,and physical verification. Troubleshoot a wide variety of design and flowcomplicated issues, and apply proactive intervention Collaborate with RTL, DFT and Circuitdesigners to ensure the high quality of design implementation and optimization. Minimum requirements: BS in Engineering or Science. Power user of EDA tools from Synopsys (ICC/DC/PT/STAR-RC),Cadence (EDI/EPS) or Mentor (Olympus-SOC). Experience in Clock/Power Distribution, P&R, Timing closure,RC Extraction, and verification on 40nm, or 28nm technology. years of experience in above areas. Prefer Requirements: MS in Engineering or Science. Knowledge in 20nm or FinFET technology, circuit design, andpackage design. Experience in physical verification tools from Synopsys(ICV/Mojave) or Mentor (Calibre). Proficiency in Perl, TCL and Makefile scripts. Tracy Wu APAC StaffingTeam Mail: tracyw@nvidia.com QQ: 1751315121 0
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