完善资料让更多小伙伴认识你,还能领取20积分哦, 立即完善>
看到夏宇闻书中的10010序列检测代码,自己写了一个三段式的FSM,并减少了两个状态,代码如下:
module _10010_detection(z,x,rst,clk); input x,clk,rst; output z; reg z; reg [2:0] cstate,nstate; parameter s0=3'd0,s1=3'd1,s2=3'd2,s3=3'd3, s4=3'd4,s5=3'd5; always @ (posedge clk) begin if(!rst) cstate<=s0; else cstate<=nstate; end always @(cstate or x) begin cstate=3'dx; case(cstate) s0:begin if(x==1) nstate=s1; else nstate=s0; end s1:begin if(x==0) nstate=s2; else nstate=s1; end s2:begin if(x==0) nstate=s3; else nstate=s1; end s3:begin if(x==1) nstate=s4; else nstate=s0; end s4:begin if(x==0) nstate=s5; else nstate=s1; end s5:begin if(x==1) nstate=s1; else nstate=s3; end default: nstate=s0; endcase end always @(posedge clk) begin if(!rst) z<=0; else begin if(nstate==s5) z<=1; else z<=0; end end endmodule testbench: `include "10010.v" module _10010_tst; reg clk,rst; reg [19:0] data; wire x,z; assign x=data[19]; initial begin clk=0; rst=0; #120 rst=1; data=20'b1100_1001_0000_1001_0100; #10000 $stop; end always @ (posedge clk) begin #2 data={data[18:0],data[19]}; end always #50 clk=~clk; _10010_detection tst(.clk(clk),.rst(rst),.x(x),.z(z)); endmodule 用modelsim仿真时,输出z始终为0,个人感觉代码应该是没问题,求指出问题所在。 |
|
相关推荐
4 个讨论
|
|
|
|
|
|
只有小组成员才能发言,加入小组>>
小黑屋| 手机版| Archiver| 电子发烧友 ( 湘ICP备2023018690号 )
GMT+8, 2024-11-29 18:59 , Processed in 0.703359 second(s), Total 77, Slave 58 queries .
Powered by 电子发烧友网
© 2015 bbs.elecfans.com
关注我们的微信
下载发烧友APP
电子发烧友观察
版权所有 © 湖南华秋数字科技有限公司
电子发烧友 (电路图) 湘公网安备 43011202000918 号 电信与信息服务业务经营许可证:合字B2-20210191 工商网监 湘ICP备2023018690号