[问答]

ADS1675高速模式采样程序，倍频不上去怎么解决？

问答对人有帮助，内容完整，我也想知道答案 0 真心求救一下工程师们，ADS1675高速模式采样程序，感觉自己写的没有问题，现在问题主要是倍频不上去，求工程师们帮忙看一下程序！ ---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 08:53:13 06/10/2019 -- Design Name: -- Module Name: ADC1675_1 - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity ADC1675_1 is Port ( AD_CLK : in STD_LOGIC; --ADC时钟输入 CS : out STD_LOGIC; START_1 : out STD_LOGIC; DRATE_0 : out STD_LOGIC; DRATE_1 : out STD_LOGIC; DRATE_2 : out STD_LOGIC; FPATH : out STD_LOGIC; LL_CONFIG : out STD_LOGIC; LVDS : out STD_LOGIC; SCLK_SEL : out STD_LOGIC; PDWN : out STD_LOGIC; ADOUT : out STD_LOGIC_VECTOR(23 downto 0); ADC_DRDY : in STD_LOGIC; -- DRDY : in STD_LOGIC; -- /DRDY_1 AD_DOUT : in STD_LOGIC; -- DOUT : in STD_LOGIC; --/DOUT_1 AD_SCLK : in STD_LOGIC -- SCLK_N : in STD_LOGIC --/SCLK_1 ); end ADC1675_1; architecture Behavioral of ADC1675_1 is type states is (init,start,decide_2,data,work); signal state : states := init; type states1 is (clk_int,delay,clk_wait,clk_star); signal state1 : states1 := clk_int; signal START_11 : std_logic; signal datreg_value : std_logic_vector (23 downto 0); --24位数据 signal acqdat_count : std_logic_vector(4 downto 0);--采集数据计数 signal counter : std_logic_vector(10 downto 0); --PLL延时计数 signal one : std_logic; signal two : std_logic; signal three : std_logic; signal four : std_logic; signal five : std_logic; signal six : std_logic; signal seven : std_logic; signal eight : std_logic; signal nine : std_logic; signal ten : std_logic; signal eleven : std_logic; signal twelve : std_logic; signal thirteen : std_logic; signal fourteen : std_logic; signal fifteen : std_logic; signal sixteen : std_logic; signal seventeen : std_logic; signal eighteen : std_logic; signal nineteen : std_logic; signal twenty : std_logic; signal twenty_one : std_logic; signal twenty_two : std_logic; signal twenty_three : std_logic; signal twenty_four : std_logic; begin process (AD_CLK) begin IF (AD_CLK'event and AD_CLK = '1') then --启动配置 case state1 is when clk_int => PDWN <= '1';--上电 CS <= '0';--芯片未选择单通道 DRATE_0 <= '1'; -- 控 DRATE_1 <= '0'; -- 制 DRATE_2 <= '1'; -- 速度 FPATH <= '0'; -- LL_CONFIG <= '1'; LVDS <= '0'; SCLK_SEL <= '0'; START_11 <= '0'; state1 <= delay; when delay => if(counter = "11111100000") then counter <= "00000000000"; state1 <= clk_wait; else counter <= counter +1; state1 <= delay; end if; when clk_wait => if(ADC_DRDY='1') then START_11 <= '1'; state1 <= clk_star; else START_11 <= '0'; state1 <= clk_wait; end if; when clk_star => START_11 <= '1'; state1 <= clk_star; end case; end IF; end process; process (AD_SCLK) begin IF (AD_SCLK'event and AD_SCLK = '1') then case state is when init => acqdat_count <= "00000"; datreg_value <= X"000000"; state <= start; when start => if (START_11 = '1') then START_1 <= '1'; state <= decide_2; else START_1 <= '0'; state <= start; end if; when decide_2 => if(ADC_DRDY = '1') then twenty_four <= AD_DOUT; acqdat_count <= "00001"; state <= work; else state <=decide_2; end if; when work => case acqdat_count is -- when "00000"=> -- twenty_four <= AD_DOUT; acqdat_count <= "00001"; state <= decide_2; --1 when "00001"=> twenty_three <= AD_DOUT; acqdat_count <= "00010"; state <= work; when "00010"=> twenty_two <= AD_DOUT; acqdat_count <= "00011"; state <= work; when "00011"=> twenty_one <= AD_DOUT; acqdat_count <= "00100"; state <= work; when "00100"=> twenty <= AD_DOUT; acqdat_count <= "00101"; state <= work; when "00101"=> nineteen <= AD_DOUT; acqdat_count <= "00110"; state <= work; when "00110"=> eighteen <= AD_DOUT; acqdat_count <= "00111"; state <= work; when "00111"=> seventeen <= AD_DOUT; acqdat_count <= "01000"; state <= work; when "01000"=> sixteen <= AD_DOUT; acqdat_count <= "01001"; state <= work; when "01001"=> fifteen <= AD_DOUT; acqdat_count <= "01010"; state <= work; --10 when "01010"=> fourteen <= AD_DOUT; acqdat_count <= "01011"; state <= work; when "01011"=> thirteen <= AD_DOUT; acqdat_count <= "01100"; state <= work; when "01100"=> twelve <= AD_DOUT; acqdat_count <= "01101"; state <= work; when "01101"=> eleven <= AD_DOUT; acqdat_count <= "01110"; state <= work; when "01110"=> ten <= AD_DOUT; acqdat_count <= "01111"; state <= work; --15 when "01111"=> nine <= AD_DOUT; acqdat_count <= "10000"; state <= work; when "10000"=> eight <= AD_DOUT; acqdat_count <= "10001"; state <= work; when "10001"=> seven <= AD_DOUT; acqdat_count <= "10010"; state <= work; when "10010"=> six <= AD_DOUT; acqdat_count <= "10011"; state <= work; --19 when "10011"=> five <= AD_DOUT; acqdat_count <= "10100"; state <= work; when "10100"=> four <= AD_DOUT; acqdat_count <= "10101"; state <= work; when "10101"=> three <= AD_DOUT; acqdat_count <= "10110"; state <= work; when "10110"=> two <= AD_DOUT; acqdat_count <= "10111"; state <= work; when "10111"=> one <= AD_DOUT; acqdat_count <= "00000"; state <=data; when others => null; end case; when data => ADOUT <= twenty_four&twenty_three&twenty_two&twenty_one&twenty&nineteen&eighteen&seventeen&sixteen&fifteen&fourteen&thirteen&twelve&eleven&ten& nine&eight&seven&six&five&four&three&two&one; state <= decide_2; end case; end IF; end process; end Behavioral; 0 本主题由 Harmony技术专家于 2024-12-10 14:50 审核通过
2024-12-10 07:51:49　　评论淘帖0 邀请回答您可以邀请以下用户，快速回答问题 × 新星之火12138 该类别下有 58 个回答。邀请回答 heks 该类别下有 57 个回答。邀请回答普罗旺斯的薰衣草该类别下有 55 个回答。邀请回答 lksas 该类别下有 46 个回答。邀请回答 wang21cj 该类别下有 45 个回答。邀请回答 chm5 该类别下有 44 个回答。邀请回答 hgimtk 该类别下有 43 个回答。邀请回答 ggfx 该类别下有 41 个回答。邀请回答 fdhsfagd 该类别下有 40 个回答。邀请回答颜刚YanG 该类别下有 40 个回答。邀请回答 zhhx1985 该类别下有 39 个回答。邀请回答 K_Ming 该类别下有 39 个回答。邀请回答潘涛12345 该类别下有 39 个回答。邀请回答 kghfh 该类别下有 39 个回答。邀请回答 huzp_bbs 该类别下有 39 个回答。邀请回答 zhouxk 该类别下有 39 个回答。邀请回答 msvdsufsdf 该类别下有 38 个回答。邀请回答 HengDu 该类别下有 38 个回答。邀请回答站着幻想该类别下有 38 个回答。邀请回答 lifei639156 该类别下有 37 个回答，其中被选为最佳答案 1 次。邀请回答举报 efwedfd 相关推荐 • LVDS隔离芯片ADN4650采集信号有误是什么原因造成的？ 279 • 电流调不上去 1476 • 为什么我用esp8266做TCP服务器网络调试助手一直连接不上去？ 9537 • keil4 没有f030的芯片从官网下载也安装不上去是什么原因？ 3261 • 请问AD7606连续采样，采样频率上不去是什么原因？ 4893 • 电机加载运行不正常，空转运行电流小，转速也加不上去 5684 • 为什么Sigma-delta ADC时钟频率提不上去？ 2310 • 请问Allegro图1到图2用slide功能最后一小段推挤不上去怎么办？ 2476 • stm32f103zet6开发板为什么会焊接不上去 1808 • 高速率的逐次逼近模数转换器ADS8412是如何设计的？ 1775 1个回答

答案对人有帮助，有参考价值 0 您好！根据您的描述，您在使用ADS1675高速模式采样程序时遇到了倍频无法提升的问题。为了帮助您解决这个问题，我需要查看您的代码。请您提供您的代码，以便我能够更好地了解您的问题并提供相应的解决方案。以下是一些建议，您可以尝试检查以下几点： 1. 确保您的代码中正确设置了ADS1675的控制寄存器，以实现高速模式采样。例如，您需要设置正确的采样率、输入通道和增益。 2. 检查您的代码中是否有任何可能导致倍频无法提升的错误。例如，检查您的代码中是否有任何逻辑错误或者错误的寄存器配置。 3. 确保您的硬件连接正确，包括电源、地线和数据线。错误的硬件连接可能导致倍频无法提升。 4. 检查您的代码中是否有任何可能导致程序运行不稳定的因素。例如，检查您的代码中是否有任何死循环或者错误的中断处理。 5. 如果您使用的是外部时钟源，请确保时钟源的频率和相位正确。错误的时钟源设置可能导致倍频无法提升。请您提供您的代码，以便我能够更好地了解您的问题并提供相应的解决方案。谢谢！

2024-12-10 18:09:41 评论举报周必镜