求助，关于TLV320AIC3254初始化配置问题求解

你好，之前没有接触过DAC的芯片，对这个不是很熟悉，我现在有个蓝牙音响须要用到这个芯片TLV320AIC3254来处理I2S DAC转换 蓝牙这边是从模式，AIC3254是主模式，我现在贴这个初始表出来请大家帮我改一下这个配置（
//DAC 2S master mode i 24BIT/192ksps Sample Rate and High Performance.
//AVdd = 1.8V, DVdd = 1.8V
///MCLK = 12.288MHz
//
）就行了其它我自己改，
static const reg_value REG_Section_program[] = {
{ 0,0x00},
// # reg[ 0][ 1] = 0x01 ; Initialize the device through software reset
{ 1,0x01},
{254,0x0A},
{ 0,0x01},
// # reg[ 1][ 1] = 0x08 ; Power up AVDD LDO; Disable weak AVDD to DVDD connection; Enable Master Analog Power Control, AVDD LDO Powered; Disable weak AVDD to DVDD connection
{ 1,0x08},
// # reg[ 1][ 2] = 0x00 ; Enable Master Analog Power Control
{ 2,0x00},
// # reg[ 1][ 71] = 0x32 ; Set the input power-up time to 3.1ms
{ 71,0x32},
// # reg[ 1][123] = 0x01 ; Set REF charging time to 40ms (automatic)
{123,0x01},
{255,0x00},
{255,0x01},
{ 0,0x00},
// # reg[ 0][ 60] = 0x00 ; DAC prog Mode: miniDSP_A and miniDSP_D NOT powered up together, miniDSP_A used for signal processing
{ 60,0x00},
// # reg[ 0][ 61] = 0x00 ; Use miniDSP_A for signal processing
{ 61,0x00},
// # reg[ 0][ 17] = 0x08 ; 8x Interpolation
{ 17,0x08},
// # reg[ 0][ 23] = 0x04 ; 4x Decimation
{ 23,0x04},
//
{ 15,0x03},
//
{ 16,0x88},
//
{ 21,0x03},
//
{ 22,0x88},
{ 0,0x08},
// # reg[ 8][ 1] = 0x04 ; adaptive mode for ADC
{ 1,0x04},
{ 0,0x2C},
// # reg[ 44][ 1] = 0x04 ; adaptive mode for DAC
{ 1,0x04},
{ 0,0x00},
// # reg[ 0][ 5] = 0x91 ; P=1, R=1, J=8
{ 5,0x91},
// # reg[ 0][ 6] = 0x08 ; P=1, R=1, J=8
{ 6,0x08},
// # reg[ 0][ 7] = 0x00 ; D=0000 (MSB)
{ 7,0x00},
// # reg[ 0][ 8] = 0x00 ; D=0000 (LSB)
{ 8,0x00},
// # reg[ 0][ 4] = 0x03 ; PLL_clkin = MCLK, codec_clkin = PLL_CLK, PLL on
{ 4,0x03},
// # reg[ 0][ 12] = 0x88 ; MDAC = 8, divider powered on
{ 12,0x88},
// # reg[ 0][ 13] = 0x00 ; DOSR = 128 (MSB)
{ 13,0x00},
// # reg[ 0][ 14] = 0x80 ; DOSR = 128 (LSB)
{ 14,0x80},
// # reg[ 0][ 18] = 0x02 ; NADC = 2, divider powered off
{ 18,0x02},
// # reg[ 0][ 19] = 0x88 ; MADC = 8, divider powered on
{ 19,0x88},
// # reg[ 0][ 20] = 0x80 ; AOSR = 128
{ 20,0x80},
// # reg[ 0][ 11] = 0x82 ; NDAC = 2, divider powered on
{ 11,0x82},
{ 0,0x01},
// # reg[ 1][ 51] = 0x40 ; Mic Bias enabled, Source = Avdd, 1.25V
{ 51,0x40},
// # reg[ 1][ 52] = 0x40 ; Route IN2L to LEFT_P with 10K input impedance; Route CM1L to LEFT_M with 10K input impedance; Route IN2R to RIGHT_P with 10K input impedance; Route IN1L to LEFT_P with 10K input impedance
{ 52,0x40},
// # reg[ 1][ 54] = 0x40 ; Route CM1L to LEFT_M with 10K input impedance
{ 54,0x40},
// # reg[ 1][ 55] = 0x40 ; Route IN1R to RIGHT_P with 10K input impedance
{ 55,0x40},
// # reg[ 1][ 57] = 0x40 ; Route CM1R to RIGHT_M with 10K input impedance
{ 57,0x40},
// # reg[ 1][ 59] = 0x00 ; Enable MicPGA_L Gain Control, 0dB
{ 59,0x00},
// # reg[ 1][ 60] = 0x00 ; Enable MicPGA_R Gain Control, 0dB
{ 60,0x00},
{ 0,0x00},
// # reg[ 0][ 81] = 0xc0 ; Power up LADC/RADC
{ 81,0xC0},
// # reg[ 0][ 82] = 0x00 ; Unmute LADC/RADC
{ 82,0x00},
{ 0,0x01},
// # reg[ 1][ 20] = 0x25 ; De-pop: 5 time constants, 6k resistance
{ 20,0x25},
// # reg[ 1][ 12] = 0x08 ; Route LDAC to HPL
{ 12,0x08},
// # reg[ 1][ 13] = 0x08 ; Route RDAC to HPR
{ 13,0x08},
// # reg[ 1][ 14] = 0x08 ; Route LDAC to LOL
{ 14,0x08},
// # reg[ 1][ 15] = 0x08 ; Route LDAC to LOR
{ 15,0x08},
{ 0,0x00},
// # reg[ 0][ 63] = 0xd4 ; Power up LDAC/RDAC w/ soft stepping
{ 63,0xD4},
{ 0,0x01},
// # reg[ 1][ 16] = 0x00 ; Unmute HPL driver, 0dB Gain
{ 16,0x00},
// # reg[ 1][ 17] = 0x00 ; Unmute HPR driver, 0dB Gain
{ 17,0x00},
// # reg[ 1][ 18] = 0x00 ; Unmute LOL driver, 0dB Gain
{ 18,0x00},
// # reg[ 1][ 19] = 0x00 ; Unmute LOR driver, 0dB Gain
{ 19,0x00},
// # reg[ 1][ 9] = 0x3c ; Power up HPL/HPR and LOL/LOR drivers
{ 9,0x3C},
{ 0,0x00},
// # reg[ 0][ 64] = 0x00 ; Unmute LDAC/RDAC
{ 64,0x00},
// # reg[0][82] = 0
{ 82,0x00},
// # reg[0][83] = 0
{ 83,0x00},
// # reg[0][86] = 32
{ 86,0x20},
// # reg[0][87] = 254
{ 87,0xFE},
// # reg[0][88] = 0
{ 88,0x00},
// # reg[0][89] = 104
{ 89,0x68},
// # reg[0][90] = 168
{ 90,0xA8},
// # reg[0][91] = 6
{ 91,0x06},
// # reg[0][92] = 0
{ 92,0x00},
// # reg[0][84] = 0
{ 84,0x00},
// # reg[0][94] = 32
{ 94,0x20},
// # reg[0][95] = 254
{ 95,0xFE},
// # reg[0][96] = 0
{ 96,0x00},
// # reg[0][97] = 104
{ 97,0x68},
// # reg[0][98] = 168
{ 98,0xA8},
// # reg[0][99] = 6
{ 99,0x06},
// # reg[0][100] = 0
{100,0x00},
}