新手入门的简单小例子-04-2 建模实现

如下图：

图1 对应的时钟与BPS的关系以及发送的逻辑

图2 对应的数据与BPS的对应关系

图3 要求的循环发送以及时间

对应的具体代码段如下：

module UART_transmit(
input wire clk,
input wire rst_n,
input wire [7:0] data,   //外部输入需要发送的数据

output reg uart_tx,
output reg led
  );

parameter CNT_1S_MAX  = 26'd50_000_000 - 1;
parameter BPS_CNT_MAX = 16'd5208 - 1;       //波特率的周期


reg [25:0] counter1;
reg        uart_state; // 0 busy 1 free
reg [3:0]  bit_counter;
reg [15:0] bps_counter;
reg        bit_flag;
reg [7:0]  data_req;


//对应的1S计数
always @(posedge clk or negedge rst_n)
 if( rst_n == 1'b0 )
   counter1 <= 26'b0;
 else if( counter1 == CNT_1S_MAX )
   counter1 <= 26'b0;
 else 
   counter1 <= counter1 + 1'b1;

//UART发送状态使能模块
always @(posedge clk or negedge rst_n)
 if( rst_n == 1'b0 )
   uart_state <= 1'b0;
 else if( counter1 == CNT_1S_MAX || (bit_counter == 4'd10 && bps_counter == BPS_CNT_MAX) )
   uart_state <= ~uart_state;
 else 
   uart_state <= uart_state;

//锁定外部输入的发送数据
always @(posedge clk or negedge rst_n)
 if( rst_n == 1'b0 )
   data_req <= 8'b0;
 else if( counter1 == CNT_1S_MAX )
   data_req <= data;
 else 
   data_req <= data_req;

//生成波特率发送信号
always @(posedge clk or negedge rst_n)
 if( rst_n == 1'b0 )
   bps_counter <= 16'b0;
 else if( uart_state == 1'b1 )begin
   if ( bps_counter == BPS_CNT_MAX ) begin
      bps_counter <= 16'b0;
   end
   else 
      bps_counter <= bps_counter + 1'b1;
 end  
 else 
   bps_counter <= 16'b0;

//单位数据发送的标志信号
always @(posedge clk or negedge rst_n)
 if( rst_n == 1'b0 )
   bit_flag <= 1'b0;
 else if( bps_counter == 16'd2603 )
   bit_flag <= 1'b1;
 else 
   bit_flag <= 1'b0;

//bit计数
always @(posedge clk or negedge rst_n)
 if( rst_n == 1'b0 )
   bit_counter <= 4'b0;
 else if( uart_state == 1'b1 ) begin
   if( bit_flag == 1'b1 )
     bit_counter <= bit_counter + 1'b1;
   else if( bit_counter == 4'd10 && bps_counter == BPS_CNT_MAX )
     bit_counter <= 4'b0;
 end
 else  
   bit_counter <= 4'b0;

//逐位发送数据
always @(posedge clk or negedge rst_n)begin
 if( rst_n == 1'b0 )begin
   uart_tx <= 1'b1;
 end    
 else begin
  case( bit_counter ) 
   0 : uart_tx <= 1'b1;
   1 : uart_tx <= 1'b0; 
   2 : uart_tx <= data_req[0];
   3 : uart_tx <= data_req[1];
   4 : uart_tx <= data_req[2];
   5 : uart_tx <= data_req[3];
   6 : uart_tx <= data_req[4];
   7 : uart_tx <= data_req[5];
   8 : uart_tx <= data_req[6];
   9 : uart_tx <= data_req[7];
   10: uart_tx <= 1'b1;
   default : uart_tx <= 1'b1;  
 endcase
 end
end

//变更LED状态
always @(posedge clk or negedge rst_n)
 if( rst_n == 1'b0 )
   led <= 1'b0;
 else if( bit_counter == 4'd10 && bps_counter == BPS_CNT_MAX )
   led <= ~led;
 else 
   led <= led;

endmodule

对应的测试用的code，如下：

`timescale 1ns/1ns

module tb_UART_transmit();

//****************** Parameter and Internal Signal *******************//
//wire define
wire   led;
wire   uart_tx;

//reg define
reg clk;
reg rst_n;
reg [7:0] data;

//***************************** Main Code ****************************//
initial begin
  rst_n <= 1'b0;
  data  <= 8'b1010_1010;
  #201
  rst_n <= 1'b1;
  #300_000_00;
  data  <= 8'b0101_0101;
  #300_000_00;
  $stop; 
end  

// creator clk
initial clk    = 1'b1;
always #10 clk <= ~clk;

defparam UART_transmit_inst.CNT_1S_MAX  = 26'd500_000 - 1;

//*************************** Instantiation **************************//

UART_transmit  UART_transmit_inst
(
.clk       ( clk     ),
.rst_n     ( rst_n   ),
.data      ( data    ),

.led       ( led ),
.uart_tx ( uart_tx )
);

endmodule

对应的仿真图，如下：