使用quilt打了一个patch,原本patch最高到0307.我这个则起名为0308-to-mt7688-3uart.patch
0308-to-mt7688-3uart.7z
除了打patch外,还需要做两件事,
1.kernel_menucofnig, one port only
2.kernel_menuconfig, 将串口数量改为3
接下来,3个串口全部可用,值得一提的是,uart2是映射到GPIO18和GPIO19上。
点击(此处)折叠或打开
--- a/arch/mips/ralink/cmdline.c
+++ b/arch/mips/ralink/cmdline.c
[url=home.php?mod=space&uid=1999721]@@[/url] -43,7 +43,7 @@
#if defined (CONFIG_RT2880_ROOTFS_IN_FLASH)
#ifdef CONFIG_SYSFS
-char rt2880_cmdline[]="console=ttyS1,57600n8 root=/dev/mtdblock5";
+char rt2880_cmdline[]="console=ttyS0,57600n8 root=/dev/mtdblock5";
#else
char rt2880_cmdline[]="console=ttyS1,57600n8 root=1f05";
#endif
--- a/arch/mips/ralink/init.c
+++ b/arch/mips/ralink/init.c
@@ -635,7 +635,7 @@ void prom_init_sysclk(void)
** To get the correct baud_base value, prom_init_sysclk() must be called before
** this function is called.
*/
-static struct uart_port serial_req[2];
+static struct uart_port serial_req[3];
__init int prom_init_serial_port(void)
{
@@ -647,7 +647,7 @@ __init int prom_init_serial_port(void)
serial_req[0].type = PORT_16550A;
serial_req[0].line = 0;
serial_req[0].irq = SURFBOARDINT_UART;
serial_req[0].irq = SURFBOARDINT_UART_LITE1;
serial_req[0].flags = UPF_FIXED_TYPE;
#if defined (CONFIG_RALINK_RT3883) || defined (CONFIG_RALINK_RT3352) || defined (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_RT6855) || defined (CONFIG_RALINK_MT7620) || defined (CONFIG_RALINK_MT7628)
serial_req[0].uartclk = 40000000;
@@ -663,12 +663,12 @@ __init int prom_init_serial_port(void)
serial_req[0].iotype = UPIO_AU;
#endif
serial_req[0].regshift = 2;
serial_req[0].mapbase = RALINK_UART_BASE;
serial_req[0].membase = ioremap_nocache(RALINK_UART_BASE, PAGE_SIZE);
serial_req[0].mapbase = RALINK_UART_LITE1_BASE;
serial_req[0].membase = ioremap_nocache(RALINK_UART_LITE1_BASE, PAGE_SIZE);
serial_req[1].type = PORT_16550A;
serial_req[1].line = 1;
serial_req[1].irq = SURFBOARDINT_UART1;
serial_req[1].irq = SURFBOARDINT_UART_LITE2;
serial_req[1].flags = UPF_FIXED_TYPE;
#if defined (CONFIG_RALINK_RT3883) || defined (CONFIG_RALINK_RT3352) || defined (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_RT6855) || defined (CONFIG_RALINK_MT7620) || defined (CONFIG_RALINK_MT7628)
serial_req[1].uartclk = 40000000;
@@ -684,11 +684,22 @@ __init int prom_init_serial_port(void)
serial_req[1].iotype = UPIO_AU;
#endif
serial_req[1].regshift = 2;
- serial_req[1].mapbase = RALINK_UART_LITE_BASE;
- serial_req[1].membase = ioremap_nocache(RALINK_UART_LITE_BASE, PAGE_SIZE);
-
serial_req[1].mapbase = RALINK_UART_LITE2_BASE;
-
serial_req[1].membase = ioremap_nocache(RALINK_UART_LITE2_BASE, PAGE_SIZE);
-
/* added by mango 20150811 */
-
serial_req[2].type = PORT_16550A;
-
serial_req[2].line = 2;
-
serial_req[2].irq = SURFBOARDINT_UART_LITE3;
-
serial_req[2].flags = UPF_FIXED_TYPE;
-
serial_req[2].uartclk = 40000000;
-
serial_req[2].iotype = UPIO_MEM32;
-
serial_req[2].regshift= 2;
-
serial_req[2].mapbase = RALINK_UART_LITE3_BASE;
-
serial_req[2].membase = ioremap_nocache(RALINK_UART_LITE3_BASE,PAGE_SIZE);
early_serial_setup(&serial_req[0]);
early_serial_setup(&serial_req[1]);
-
early_serial_setup(&serial_req[2]);
return(0);
}
@@ -751,6 +762,14 @@ static void serial_setbrg(unsigned long
DLM(RALINK_SYSCTL_BASE + 0x500) = clock_divisor >> 8;
LCR(RALINK_SYSCTL_BASE + 0x500) = UART_LCR_WLEN8;
#endif
+/mango/
- IER(RALINK_SYSCTL_BASE + 0xE00) = 0;
- FCR(RALINK_SYSCTL_BASE + 0xE00) = 0;
- LCR(RALINK_SYSCTL_BASE + 0xE00) = (UART_LCR_WLEN8 | UART_LCR_DLAB);
- DLL(RALINK_SYSCTL_BASE + 0xE00) = clock_divisor & 0xff;
- DLM(RALINK_SYSCTL_BASE + 0xE00) = clock_divisor >> 8;
- LCR(RALINK_SYSCTL_BASE + 0xE00) = UART_LCR_WLEN8;
}
--- a/drivers/char/ralink_gpio.c
+++ b/drivers/char/ralink_gpio.c
@@ -2459,7 +2459,7 @@ int __init ralink_gpio_init(void)
{
unsigned int i;
u32 gpiomode;
#ifdef CONFIG_DEVFS_FS
if (devfs_register_chrdev(ralink_gpio_major, RALINK_GPIO_DEVNAME,
&ralink_gpio_fops)) {
@@ -2492,7 +2492,22 @@ int __init ralink_gpio_init(void)
gpiomode &= ~0x2000; //clear bit[13] WLAN_LED
#endif
gpiomode |= RALINK_GPIOMODE_DFT;
-
gpiomode &=~(0x03<<26);//clear bit[27][26] uart2
*(volatile u32 *)(RALINK_REG_GPIOMODE) = cpu_to_le32(gpiomode);
-
/* added by mango 20150811 for AGPIO_MODE init */
+#if 0
- agpio_cfg = le32_to_cpu(*(volatile u32 *)(RALINK_SYSCTL_ADDR+0x3C));
- /* I2S bit3:0;1111:digital*/
- agpio_cfg |=0x0f;
- /* refclko bit4;1:digital */
- agpio_cfg |=0x01<<4;
- /* wled_OD_EN */
- /* ephy p0 */
- /* EPHY_GPIO_AIO_EN bit20:17;1111:digital */
- agpio_cfg |=0x0f<<17;
- *(volatile u32 *)(RALINK_SYSCTL_ADDR+0X3c) = cpu_to_le32(agpio_cfg);
- printk("\n\r agpio_cfg");
+#endif
*(volatile u32 *)(RALINK_REG_INTENA) = cpu_to_le32(RALINK_INTCTL_PIO);
--- a/drivers/char/ralink_gpio.h
+++ b/drivers/char/ralink_gpio.h
@@ -479,7 +479,7 @@
#define RALINK_GPIOMODE_SPI_SLAVE 0x4
#define RALINK_GPIOMODE_SPI_CS1 0x10
#define RALINK_GPIOMODE_I2S 0x40
-#define RALINK_GPIOMODE_UART1 0x100
+#define RALINK_GPIOMODE_UART1 0x000
#define RALINK_GPIOMODE_SDXC 0x400
#define RALINK_GPIOMODE_SPI 0x1000
#define RALINK_GPIOMODE_WDT 0x4000
@@ -489,8 +489,8 @@
#define RALINK_GPIOMODE_EPHY 0x40000
#define RALINK_GPIOMODE_P0LED 0x100000
#define RALINK_GPIOMODE_WLED 0x400000
-#define RALINK_GPIOMODE_UART2 0x1000000
-#define RALINK_GPIOMODE_UART3 0x4000000
+#define RALINK_GPIOMODE_UART2 0x0000000
+#define RALINK_GPIOMODE_UART3 0x0000000
#define RALINK_GPIOMODE_PWM0 0x10000000
#define RALINK_GPIOMODE_PWM1 0x40000000
@@ -505,7 +505,7 @@
#elif defined (CONFIG_RALINK_MT7620)
#define RALINK_GPIOMODE_DFT (RALINK_GPIOMODE_I2C)
#elif defined (CONFIG_RALINK_MT7628)
-#define RALINK_GPIOMODE_DFT (RALINK_GPIOMODE_UART2 | RALINK_GPIOMODE_UART3) | (RALINK_GPIOMODE_SPI_CS1) | (RALINK_GPIOMODE_WDT)
+#define RALINK_GPIOMODE_DFT (RALINK_GPIOMODE_UART2 | RALINK_GPIOMODE_UART3 | RALINK_GPIOMODE_UART1 | RALINK_GPIOMODE_SPI_CS1 | RALINK_GPIOMODE_WDT | RALINK_GPIOMODE_SPI_SLAVE )
#else
#define RALINK_GPIOMODE_DFT (RALINK_GPIOMODE_UARTF)
#endif
原作者:guangmangdz