【FPGA经典试题】FPGA的乘法运算Verilog 模块、DPRAM 的设计模块

FPGA

【FPGA经典试题】FPGA的乘法运算Verilog 模块、DPRAM 的设计模块
⑴ 请参看如下文章，写出文中的关键点；
⑵ 写出当外部同时输入了时钟和reset 信号，两个8bit 补码数的乘法运算的
Verilog 模块；
⑶ 写出当外部同时输入了时钟和reset 信号，DPRAM 的设计代码；
1.文中重要讲的事复位方式的选择会影响设计性能。乘法器和RAMs 的寄存器只
能使用同步复位。

⑵ 写出当外部同时输入了时钟和reset 信号，两个8bit 补码数的乘法运算的
Verilog 模块；

2.
module mul_8bit(clk,reset,multiplicand,multiplier,ValOut); //start
parameter width = 8;
input clk;
input reset;
//input start;
input [7:0] multiplicand;
input [7:0] multiplier;
output [15:0] ValOut;
reg [15:0] ValOut;
wire [7:0] mulD;
wire [7:0] mulR;
wire sign1,sign2,sign3,sign4;
wire one1,one2,one3,one4;
wire two1,two2,two3,two4;
//·ûºÅsign=~A[2n+1] & (A[2n]|
A[2n-1])£»sign±íÊ¾·ûºÅÎ»£¬μ±ÆäÎª1Ê±£¬Ôò²¼Ë¹±àÂëÈ¡Õý£»·´Ö®£¬È¡¸º¡£
A[-1] ²¹Áã¼´A[-1]=0
assign sign1 = ~mulR[1] & (mulR[0] | 0);
assign sign2 = ~mulR[3] & (mulR[2] | mulR[1]);
assign sign3 = ~mulR[5] & (mulR[4] | mulR[3]);
assign sign4 = ~mulR[7] & (mulR[6] | mulR[5]);
//one; one=A[2n]^A[2n-1]£»Èôone=1,Ôò²¿·Ö»ýÎªb£»·ñÔòÎª0¡£
assign one1 = mulR[0]^0;
assign one2 = mulR[2]^mulR[1];
assign one3 = mulR[4]^mulR[3];
assign one4 = mulR[6]^mulR[5];
//two=(¡«A[2n+1]&A[2n]&A[2n-1])|(A[2n+1]&¡«A[2n]&¡«A[2n-1])£»ÈôtwoÎª1£¬Ô
ò²¿·Ö»ýÎª2b£»·ñÔòÎª0¡£
assign two1 = (~mulR[1] & mulR[0] & 0)|(mulR[1] & ~mulR[0] & 1);
assign two2 = (~mulR[3] & mulR[2] & mulR[1])|(mulR[3] & ~mulR[2] &
~mulR[1]);
assign two3 = (~mulR[5] & mulR[4] & mulR[3])|(mulR[5] & ~mulR[4] &
~mulR[3]);
assign two4 = (~mulR[7] & mulR[6] & mulR[5])|(mulR[7] & ~mulR[6] &
~mulR[5]);
//·ûºÅÀ©Õ¹
wire [15:0] temp;
assign temp = {{8{mulD[7]}},mulD[7:0]};
// ¼ÆËãÊä³ö
wire [15:0] dat_w1,dat_w2,dat_w3,dat_w4;
//- 2 * B = = (~ (B << 1)) + 1 ;2B= (B<<1);
assign dat_w1 = (two1) ? ((sign1) ? {temp[14:0],1'b0}:(~{temp[14:0],1'b0} + 1'b1 ) ) :
((one1) ? ((sign1) ? temp :{~temp+1'b1} ) : 0);
assign dat_w2 = (two2) ? ((sign2) ? {temp[14:0],1'b0}: (~{temp[14:0],1'b0} + 1'b1 )) :
((one2) ? ((sign2) ? temp :{~temp+1'b1} ) : 0);
assign dat_w3 = (two3) ? ((sign3) ? {temp[14:0],1'b0}:(~{temp[14:0],1'b0} + 1'b1 ) ) :
((one3) ? ((sign3) ? temp :{~temp+1'b1} ) : 0);
assign dat_w4 = (two4) ? ((sign4) ? {temp[14:0],1'b0}:(~{temp[14:0],1'b0} + 1'b1 ) ) :
((one4) ? ((sign4) ? temp :{~temp+1'b1}) : 0);
//assign ValOut = dat_w1 + {dat_w2[13:0],2'b00} + {dat_w3[11:0],4'b0000} +
{dat_w4[9:0],6'b000000};
assign mulD = multiplicand;
assign mulR = multiplier;
always @(posedge clk) begin
if(!reset) begin
ValOut <= 0;
end
else begin
ValOut <= dat_w1 + {dat_w2[13:0],2'b00} + {dat_w3[11:0],4'b0000}
+ {dat_w4[9:0],6'b000000};
end
end
endmodule