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请分别写出两个8bit 补码数的加法和乘法运算的Verilog 模块。(提示:注意补
码的处理,支持Verilog2001 国际规范)
注意:输入信号和输出信号都是补码表示的数。
- module adder(A,B,SUM);
- input[7:0] A,B;
- // input cin; // cin cout,overflow
- output[7:0] SUM;
- // output cout,overflow;
- wire [6:0] c;
- // È«¼ÓÆ÷Âß¼-·½³Ìʽ
- assign SUM[0] = A[0]^B[0]^0,//cin,
- c[0] = (A[0] & B[0])|(B[0] & 0)|(A[0] & 0);
- assign SUM[1] = A[1]^B[1]^c[0],
- c[1] = (A[1] & B[1])|(B[1] & c[0])|(A[1] & c[0]);
- assign SUM[2] = A[2]^B[2]^ c[1],
- c[2] = (A[2] & B[2])|(B[2] & c[1])|(A[2] & c[1]);
- assign SUM[3] = A[3]^B[3]^ c[2],
- c[3] = (A[3] & B[3])|(B[3] & c[2])|(A[3] & c[2]);
- assign SUM[4] = A[4]^B[4]^c[3],
- c[4] = (A[4] & B[4])|(B[4] & c[3])|(A[4] & c[3]);
- assign SUM[5] = A[5]^B[5]^ c[4],
- c[5] = (A[5] & B[5])|(B[5] & c[4])|(A[5] & c[4]);
- assign SUM[6] = A[6]^B[6]^ c[5],
- c[6] = (A[6] & B[6])|(B[6] & c[5])|(A[6] & c[5]);
- assign SUM[7] = A[7]^B[7]^ c[6];
- // cout = (A[7] & B[7])|(B[7] & c[6])|(A[7] & c[6]);
- //
- //assign overflow = cout^c[6];
- endmodule
-
- 补码乘法器:
- module mul_8bit(multiplicand,multiplier,ValOut); //start
- parameter width = 8;
- //input start;
- input [7:0] multiplicand;
- input [7:0] multiplier;
- output [15:0] ValOut;
- wire [7:0] mulD;
-
- wire [7:0] mulR;
- wire sign1,sign2,sign3,sign4;
- wire one1,one2,one3,one4;
- wire two1,two2,two3,two4;
- //·ûºÅsign=~A[2n+1] & (A[2n]|
- A[2n-1])£»sign±íʾ·ûºÅ룬μ±ÆäΪ1ʱ£¬Ôò²¼Ë¹±àÂëÈ¡Õý£»·´Ö®£¬È¡¸º¡£ A[-1]
- ²¹Áã¼´A[-1]=0
- assign sign1 = ~mulR[1] & (mulR[0] | 0);
- assign sign2 = ~mulR[3] & (mulR[2] | mulR[1]);
- assign sign3 = ~mulR[5] & (mulR[4] | mulR[3]);
- assign sign4 = ~mulR[7] & (mulR[6] | mulR[5]);
- //one; one=A[2n]^A[2n-1]£»Èôone=1,Ôò²¿·Ö»ýΪb£»·ñÔòΪ0¡£
- assign one1 = mulR[0]^0;
- assign one2 = mulR[2]^mulR[1];
- assign one3 = mulR[4]^mulR[3];
- assign one4 = mulR[6]^mulR[5];
- //two
- two=(¡«A[2n+1]&A[2n]&A[2n-1])|(A[2n+1]&¡«A[2n]&¡«A[2n-1])£»ÈôtwoΪ1£¬Ôò²¿·Ö»ýÎ
- ª2b£»·ñÔòΪ0¡£
- assign two1 = (~mulR[1] & mulR[0] & 0)|(mulR[1] & ~mulR[0] & 1);
- assign two2 = (~mulR[3] & mulR[2] & mulR[1])|(mulR[3] & ~mulR[2] & ~mulR[1]);
- assign two3 = (~mulR[5] & mulR[4] & mulR[3])|(mulR[5] & ~mulR[4] & ~mulR[3]);
- assign two4 = (~mulR[7] & mulR[6] & mulR[5])|(mulR[7] & ~mulR[6] & ~mulR[5]);
- //·ûºÅÀ©Õ¹
- wire [15:0] temp;
- assign temp = {{8{mulD[7]}},mulD[7:0]};
- // ¼ÆËãÊä³ö
- wire [15:0] dat_w1,dat_w2,dat_w3,dat_w4;
- //- 2 * B = = (~ (B << 1)) + 1 ;2B= (B<<1);
- assign dat_w1 = (two1) ? ((sign1) ? {temp[14:0],1'b0}:(~{temp[14:0],1'b0} + 1'b1 ) ) : ((one1) ?
- ((sign1) ? temp :{~temp+1'b1} ) : 0);
- assign dat_w2 = (two2) ? ((sign2) ? {temp[14:0],1'b0}: (~{temp[14:0],1'b0} + 1'b1 )) : ((one2) ?
- ((sign2) ? temp :{~temp+1'b1} ) : 0);
- assign dat_w3 = (two3) ? ((sign3) ? {temp[14:0],1'b0}:(~{temp[14:0],1'b0} + 1'b1 ) ) : ((one3) ?
- ((sign3) ? temp :{~temp+1'b1} ) : 0);
-
- assign dat_w4 = (two4) ? ((sign4) ? {temp[14:0],1'b0}:(~{temp[14:0],1'b0} + 1'b1 ) ) : ((one4) ?
- ((sign4) ? temp :{~temp+1'b1}) : 0);
- assign ValOut = dat_w1 + {dat_w2[13:0],2'b00} + {dat_w3[11:0],4'b0000} +
- {dat_w4[9:0],6'b000000};
- assign mulD = multiplicand;
- assign mulR = multiplier;
- endmodule
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