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修改SetSysClock()函数,将时钟源由默认的HSE改为内部HSI时钟
system_stm32f0xx.c static void SetSysClock(void) { __IO uint32_t StartUpCounter = 0, HSIStatus = 0; /* SYSCLK, HCLK, PCLK configuration ----------------------------------------*/ /* Enable HSI */ RCC-》CR |= ((uint32_t)RCC_CR_HSION);//((uint32_t)RCC_CR_HSEON) /* Wait till HSI is ready and if Time out is reached exit */ do { HSIStatus = RCC-》CR & RCC_CR_HSIRDY;//RCC-》CR & RCC_CR_HSERDY; StartUpCounter++; } while((HSIStatus == 0) && (StartUpCounter != HSI_STARTUP_TIMEOUT)); if ((RCC-》CR & RCC_CR_HSIRDY) != RESET)//((RCC-》CR & RCC_CR_HSERDY) != RESET { HSIStatus = (uint32_t)0x01; } else { HSIStatus = (uint32_t)0x00; } if (HSIStatus == (uint32_t)0x01) { /* Enable Prefetch Buffer and set Flash Latency */ FLASH-》ACR = FLASH_ACR_PRFTBE | FLASH_ACR_LATENCY; /* HCLK = SYSCLK */ RCC-》CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; /* PCLK = HCLK */ RCC-》CFGR |= (uint32_t)RCC_CFGR_PPRE_DIV1; /* PLL configuration = HSE * 6 = 48 MHz */ /* PLL configuration = HSI/2 * 12 = 48 MHz */ RCC-》CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL)); RCC-》CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSI_DIV2| RCC_CFGR_PLLMULL12); // RCC-》CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLMULL6) /* Enable PLL */ RCC-》CR |= RCC_CR_PLLON; /* Wait till PLL is ready */ while((RCC-》CR & RCC_CR_PLLRDY) == 0) { } /* Select PLL as system clock source */ RCC-》CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); RCC-》CFGR |= (uint32_t)RCC_CFGR_SW_PLL; /* Wait till PLL is used as system clock source */ while ((RCC-》CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL) { } } else { /* If HSI fails to start-up, the application will have wrong clock configuration. User can add here some code to deal with this error */ } } |
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