Haawking DSC28027实例程序开发教程—EQEP_PWM

ti

本帖最后由阳阳阳阳阳阳阳阳于 2021-8-23 18:33 编辑

/******************************************************************

编译器：Haawking IDE V0.5.0

D S P：dsc28027勇士板

电脑配 置：Windows10 专业版; 64 位操作系统

仿真器：HX100V2

使用库：无

作 用：EQEP对PWM产生的脉冲进行测算。

采用三种测算方式：1. PulseCap脉冲捕获 2. Mspeed法 3. Tspeed_Angle法

版 本：V0.0.1

******************************************************************/

1.HaawkingIDE新建工程

2. EPWM模块配置

//##################################################################

// FILE: PWMFunctions.c

//

// Build Date: 2021.03.13

// Description: This file configures the ePWM module

//

//##################################################################

void EPWMConfig()
{
EALLOW;
SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0;
EDIS;
EPWM1_Config();
EPWM2_Config();
//EPWM3_Config();
EALLOW;
SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1;
EDIS;
}
void EPWM1_Config()
{
EALLOW;
//========================================================================
// Time-Base (TB) Submodule
//========================================================================
EPwm1Regs.TBPRD = EPWM1_TBPRD; // the period of the time-base counter
EPwm1Regs.TBPHS.half.TBPHS = 0; // the time-base counter phase
EPwm1Regs.TBCTR = 0; // the current time-base counter value
EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Counter Mode
EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Counter Register Load From Phase Register Enable
EPwm1Regs.TBCTL.bit.PRDLD = TB_SHADOW; // Active Period Register Load From Shadow Register
EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_DISABLE; // Synchronization Output Select
EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_HSPCLK_DIV1; // High Speed Time-base Clock Prescale
EPwm1Regs.TBCTL.bit.CLKDIV = TB_CLK_DIV1; // Time-base Clock Prescale
EPwm1Regs.TBCTL.bit.PHSDIR = TB_UP; // Phase Direction
EPwm1Regs.TBCTL.bit.FREE_SOFT = TB_FREE_RUN; // Emulation Mode Run Mode
//========================================================================
// Counter-Compare (CC) Submodule
//========================================================================
EPwm1Regs.CMPA.half.CMPA = Pwm1CMPA; // Set compare A value
//========================================================================
// Action-Qualifier (AQ) Submodule
//========================================================================
EPwm1Regs.AQCTLA.bit.PRD = AQ_CLEAR; // the counter equals the period.
EPwm1Regs.AQCTLA.bit.ZRO = AQ_SET; // the counter equals the zero.
EPwm1Regs.AQCTLB.bit.CAD = AQ_CLEAR; // equals CMPA and decrementing.
EPwm1Regs.AQCTLB.bit.CAU = AQ_SET; // equals CMPA and incrementing.
EPwm1Regs.AQSFRC.bit.RLDCSF = AQ_IMMEDI;
//========================================================================
// PWM-Chopper (PC) Submodule
//========================================================================
EPwm1Regs.PCCTL.bit.CHPEN = CHP_DISABLE; // PWM-chopping Enable
//========================================================================
// Trip-Zone (TZ) Submodule
//========================================================================
EPwm1Regs.TZCTL.bit.TZA = TZ_FORCE_LO; // a trip event occurs output EPWMxA action
EPwm1Regs.TZCTL.bit.TZB = TZ_FORCE_LO; // a trip event occurs output EPWMxB action
EDIS;
}
void EPWM2_Config()
{
EALLOW;
//========================================================================
// Time-Base (TB) Submodule
//========================================================================
EPwm2Regs.TBPRD = EPWM2_TBPRD; // the period of the time-base counter
EPwm2Regs.TBPHS.half.TBPHS = 0; // the time-base counter phase
EPwm2Regs.TBCTR = 0; // the current time-base counter value
EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Counter Mode
EPwm2Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Counter Register Load From Phase Register Enable
EPwm2Regs.TBCTL.bit.PRDLD = TB_SHADOW; // Active Period Register Load From Shadow Register
EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_DISABLE; // Synchronization Output Select
EPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_CLK_DIV128; // High Speed Time-base Clock Prescale
EPwm2Regs.TBCTL.bit.CLKDIV = TB_HSPCLK_DIV10; // Time-base Clock Prescale
EPwm2Regs.TBCTL.bit.PHSDIR = TB_UP; // Phase Direction
EPwm2Regs.TBCTL.bit.FREE_SOFT = TB_FREE_RUN; // Emulation Mode Run Mode
//========================================================================
// Counter-Compare (CC) Submodule
//========================================================================
EPwm2Regs.CMPA.half.CMPA = Pwm2CMPA; // Set compare A value
//========================================================================
// Action-Qualifier (AQ) Submodule
//========================================================================
EPwm2Regs.AQCTLA.bit.CAU = AQ_CLEAR; // equals CMPA and incrementing.
EPwm2Regs.AQCTLA.bit.ZRO = AQ_SET; // the counter equals the zero.
EPwm2Regs.AQSFRC.bit.RLDCSF = AQ_IMMEDI;
//========================================================================
// Trip-Zone (TZ) Submodule
//========================================================================
EPwm2Regs.TZCTL.bit.TZA = TZ_FORCE_LO; // a trip event occurs output EPWMxA action
EPwm2Regs.TZCTL.bit.TZB = TZ_FORCE_LO; // a trip event occurs output EPWMxB action
EDIS;
}

复制代码

定时器0配置：

//##################################################################

// FILE: TimerFunctions.c

// Build Date: 2021.03.14

// Description: Timer0,Timer1,Timer2

//

//##################################################################

void Timer0Config(void)
{
EALLOW;
CpuTimer0Regs.TCR.bit.TSS = 1;
CpuTimer0Regs.TCR.bit.TIF = 1;
CpuTimer0Regs.PRD.all = SysFreq*100; // 10k for 12MHz
CpuTimer0Regs.TIM.all = 0;
CpuTimer0Regs.TCR.bit.TIE = 1;
CpuTimer0Regs.TCR.bit.TSS = 0;
EDIS;
}

复制代码

EQEP模块配置：

//##################################################################

// FILE: EQEPFunctions.c

// Author: daienqiang

// Build Date: 2021.03.14

// Description: eQEP module

//

//##################################################################

void EQEPConfig()
{
#ifdef PulseCap
EALLOW;
EQep1Regs.QPOSMAX = 0xFFFFFFFF;
EQep1Regs.QUPRD = SysFreq*100;
EQep1Regs.QDECCTL.bit.QSRC = 1; // 0-Quadrature count mode, 1-Direction-count mode
EQep1Regs.QDECCTL.bit.XCR = 1; // 0-2x resolution, 1-1x resolution
EQep1Regs.QEPCTL.bit.FREE_SOFT = 3;
EQep1Regs.QEPCTL.bit.PCRM = 3; // Position counter reset on a unit time event
EQep1Regs.QEPCTL.bit.QPEN = 1; // eQEP position counter is enabled
EQep1Regs.QEPCTL.bit.QCLM = 1; // Latch on unit time out
EQep1Regs.QEPCTL.bit.UTE = 1; // Enable unit timer
EDIS;
#endif
#ifdef MSpeed
EALLOW;
EQep1Regs.QPOSMAX = 0xFFFFFFFF;
EQep1Regs.QUPRD = SysFreq*100;
EQep1Regs.QDECCTL.bit.QSRC = 0; // 0-Quadrature count mode, 1-Direction-count mode
EQep1Regs.QDECCTL.bit.XCR = 0; // 0-2x resolution, 1-1x resolution
EQep1Regs.QEPCTL.bit.FREE_SOFT = 3;
EQep1Regs.QEPCTL.bit.PCRM = 3; // Position counter reset on a unit time event
EQep1Regs.QEPCTL.bit.QPEN = 1; // eQEP position counter is enabled
EQep1Regs.QEPCTL.bit.QCLM = 1; // Latch on unit time out
EQep1Regs.QEPCTL.bit.UTE = 1; // Enable unit timer
EDIS;
#endif
#ifdef TSpeed_Angle
EALLOW;
EQep1Regs.QPOSMAX = 4000;
EQep1Regs.QUPRD = 6000;
//EQep1Regs.QPOSCMP = 1;
EQep1Regs.QDECCTL.bit.QSRC = 0; // 0-Quadrature count mode, 1-Direction-count mode
EQep1Regs.QDECCTL.bit.XCR = 0; // 0-2x resolution, 1-1x resolution
EQep1Regs.QEPCTL.bit.FREE_SOFT = 3;
EQep1Regs.QEPCTL.bit.PCRM = 1; // 0-Position counter reset on an index event, 1-the maximum position 3-on a unit time event
EQep1Regs.QEPCTL.bit.QPEN = 1; // 0-eQEP position counter is disabled , 1-eQEP position counter is enabled
EQep1Regs.QEPCTL.bit.QCLM = 1; // 0- Latch on position counter read by CPU, 1-Latch on unit time out
EQep1Regs.QEPCTL.bit.UTE = 1; // 0-disable unit timer, 1-Enable unit timer
EQep1Regs.QCAPCTL.bit.UPPS = 0; // QCLK/1
EQep1Regs.QCAPCTL.bit.CCPS = 0; // SYSCLKOUT/1
EQep1Regs.QCAPCTL.bit.CEN = 1; // 1-eQEP capture unit is enabled
EDIS;
#endif
}