EPMW1A与1B配置成互补模式不能实现同时低的解决办法？

EPMW1A与1B配置成互补模式，需要软件同时关闭1A与1B。
强制低时，不能实现同时低，实际一高一低保持互补关系。
目前软件的解决方法是，关脉冲时同时取消互补，开脉冲时打开互补。
请问应该怎么正确解决?
部分代码如下：
// EPwm Module 1 config
(*ePWM[0]).AQCSFRC.bit.CSFA = 1; // Force a continuous low on output A
(*ePWM[0]).AQCSFRC.bit.CSFB = 1; // Force a continuous low on output B
(*ePWM[0]).AQSFRC.bit.RLDCSF = 3; // Load immediately
(*ePWM[0]).TBPRD = EPWM_TBPRD_20K; // Period = Pwm_TBPRD_20K TBCLK counts
(*ePWM[0]).TBPRDHR = 0;
(*ePWM[0]).TBPHS.all = 0; // Set Phase register to zero
(*ePWM[0]).TBCTR = 0;
(*ePWM[0]).TBCTL.bit.CLKDIV = TB_DIV1; // TBCLK = SYSCLKOUT / (HSPCLKDIV × CLKDIV)
(*ePWM[0]).TBCTL.bit.HSPCLKDIV = TB_DIV1;
(*ePWM[0]).TBCTL.bit.FREE_SOFT = 11; // Emulation Mode Bits. Stop after the next time-base counter increment or decrement
(*ePWM[0]).TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Symmetrical mode
(*ePWM[0]).TBCTL.bit.PHSEN = TB_ENABLE;
(*ePWM[0]).TBCTL.bit.PRDLD = TB_SHADOW;
(*ePWM[0]).TBCTL.bit.SYNCOSEL = TB_SYNC_IN; // Sync down-stream module
(*ePWM[0]).CMPCTL.bit.SHDWAMODE = CC_SHADOW;
(*ePWM[0]).CMPCTL.bit.SHDWBMODE = CC_SHADOW;
(*ePWM[0]).CMPCTL.bit.LOADAMODE = CC_CTR_ZERO_PRD; // load on CTR=Zero and PRD
(*ePWM[0]).CMPCTL.bit.LOADBMODE = CC_CTR_ZERO_PRD; // load on CTR=Zero and PRD
(*ePWM[0]).AQCTLA.bit.CAU = AQ_SET; // set actions for EPwmA
(*ePWM[0]).AQCTLA.bit.CAD = AQ_CLEAR;
(*ePWM[0]).AQCTLB.bit.CBU = AQ_SET; // set actions for EPwmB
(*ePWM[0]).AQCTLB.bit.CBD = AQ_CLEAR;
(*ePWM[0]).DBCTL.bit.IN_MODE = DBA_ALL;
(*ePWM[0]).DBCTL.bit.OUT_MODE = DB_FULL_ENABLE; // enable Dead-band module
(*ePWM[0]).DBCTL.bit.POLSEL = DB_ACTV_HIC; // Active Hi complementary
(*ePWM[0]).DBFED = DEAD_BAND_US(4); // FED, 1us per 90 TBCLKs, 10-bit counter
(*ePWM[0]).DBRED = DEAD_BAND_US(4); // RED, 1us per 90 TBCLKs, 10-bit counter
//(*ePWM[0]).ETSEL.bit.INTEN = 1; // Enable INT
//(*ePWM[0]).ETSEL.bit.INTSEL = ET_CTR_ZERO // Select INT on Zero event
//(*ePWM[0]).ETPS.bit.INTPRD = ET_1ST; // Generate INT on 1st event
(*ePWM[0]).ETSEL.bit.SOCAEN = 1; // Enable SOC on A group
(*ePWM[0]).ETSEL.bit.SOCASEL = ET_CTR_PRD; // Enable event time-base counter equal to period. (TBCTR = PRD)
(*ePWM[0]).ETPS.bit.SOCAPRD = ET_1ST; // Generate pulse on 1st event
(*ePWM[0]).CMPA.all = 0xFFFFFF00; // Set compare A value
(*ePWM[0]).CMPB = 0xFFFF; // Set compare B value

EALLOW;
/*
(*ePWM[0]).HRCNFG.all = 0;
(*ePWM[0]).HRCNFG.bit.EDGMODE = HR_BEP; // MEP control on both edges
(*ePWM[0]).HRCNFG.bit.CTLMODE = HR_CMP; // CMPAHR and TBPRDHR HR control
(*ePWM[0]).HRCNFG.bit.HRLOAD = HR_CTR_ZERO; // load on CTR = 0
(*ePWM[0]).HRCNFG.bit.AUTOCONV = 1; // Enable autoconversion for HR period
(*ePWM[0]).HRPCTL.bit.HRPE = 0; // Turn off high-resolution period control.
(*ePWM[0]).HRCNFG.bit.SELOUTB = 0; // ePWMxB output is normal.
(*ePWM[0]).TBCTL.bit.PHSEN = 1;
(*ePWM[0]).HRPCTL.bit.TBPHSHRLOADE = 1; // Enable TBPHSHR sync (required for updwn count HR control)
*/
(*ePWM[0]).TZCTL.bit.TZA = TZ_FORCE_LO;
(*ePWM[0]).TZCTL.bit.TZB = TZ_FORCE_LO;
(*ePWM[0]).TZCLR.all = 0xFF;
EDIS;
关闭脉冲：
EPwm1Regs.DBCTL.bit.OUT_MODE = DB_DISABLE;
EPwm1Regs.AQCSFRC.bit.CSFA = 1; // Force a continuous low on output A
EPwm1Regs.AQCSFRC.bit.CSFB = 1; // Force a continuous low on output B
EPwm1Regs.AQSFRC.bit.RLDCSF = 3; // Load immediately

打开脉冲：
EPwm1Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
EPwm1Regs.CMPA.all = 0xFFFFFF00;
EALLOW;
EPwm1Regs.TZCLR.all = 0xFF;
EDIS;
EPwm1Regs.AQCSFRC.bit.CSFA = 3; // Software forcing is disabled and has no effect
EPwm1Regs.AQCSFRC.bit.CSFB = 3; // Software forcing is disabled and has no effect
EPwm1Regs.AQSFRC.bit.RLDCSF = 3; // Load immediately