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EPwm1Regs.TBPRD = 500; // Period = 500 TBCLK counts
EPwm1Regs.TBPHS.half.TBPHS = 0; // Set Phase register to zero EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Asymmetrical mode EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Master module EPwm1Regs.TBCTL.bit.PRDLD = TB_SHADOW; EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1 ; EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1; EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO; // Sync down-stream module EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW; EPwm1Regs.AQCTLA.bit.ZRO = AQ_SET; // set actions for EPWM1A EPwm1Regs.AQCTLA.bit.PRD = AQ_CLEAR; EPwm2Regs.TBPRD = 500; // Period = 500 TBCLK counts EPwm2Regs.TBPHS.half.TBPHS = 0; // Set Phase register to zero EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Asymmetrical mode EPwm2Regs.TBCTL.bit.PHSEN = TB_ENABLE; // Master module EPwm2Regs.TBCTL.bit.PRDLD = TB_SHADOW; EPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1 ; EPwm2Regs.TBCTL.bit.CLKDIV = TB_DIV1; EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; // Sync down-stream module EPwm2Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; EPwm2Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW; EPwm2Regs.AQCTLA.bit.ZRO = AQ_SET; // set actions for EPWM1A EPwm2Regs.AQCTLA.bit.PRD = AQ_CLEAR; |
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楼主你好,
设置同步以后,主同步ePWM模块和其他被同步的ePWM单元间会有计数值差,其它被同步的单元之间计数值是一样的。 这一点规格书里有详细描述如下: EPWMxSYNCI: Synchronization Input Pulse: The value of the phase register is loaded into the counter register when an input synchronization pulse is detected (TBPHS ® TBCTR). This operation occurs on the next valid time-base clock (TBCLK) edge. The delay from internal master module to slave modules is given by: – if ( TBCLK = SYSCLKOUT): 2 x SYSCLKOUT – if ( TBCLK != SYSCLKOUT):1 TBCLK |
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