[问答]

求教FPGA时序约束问题与输入信号以及PLL输出Slack为负该如何解决？

问答对人有帮助，内容完整，我也想知道答案 0 Critical Warning: No exact pin location assignment(s) for 77 pins of 80 total pins Info: Pin addr_monitor[0] not assigned to an exact location on the device Info: Pin addr_monitor[2] not assigned to an exact location on the device Info: Pin addr_monitor[4] not assigned to an exact location on the device Info: Pin addr_monitor[6] not assigned to an exact location on the device Info: Pin addr_monitor[8] not assigned to an exact location on the device Info: Pin addr_monitor[10] not assigned to an exact location on the device Info: Pin addr_monitor[12] not assigned to an exact location on the device Info: Pin data_out[0] not assigned to an exact location on the device Info: Pin data_out[2] not assigned to an exact location on the device Info: Pin data_out[4] not assigned to an exact location on the device Info: Pin data_out[6] not assigned to an exact location on the device Info: Pin max[0] not assigned to an exact location on the device Info: Pin max[2] not assigned to an exact location on the device Info: Pin max[4] not assigned to an exact location on the device Info: Pin max[6] not assigned to an exact location on the device Info: Pin max[8] not assigned to an exact location on the device Info: Pin max[10] not assigned to an exact location on the device Info: Pin max[12] not assigned to an exact location on the device Info: Pin max[14] not assigned to an exact location on the device Info: Pin max[16] not assigned to an exact location on the device Info: Pin max[18] not assigned to an exact location on the device Info: Pin max[20] not assigned to an exact location on the device Info: Pin max[22] not assigned to an exact location on the device Info: Pin max[24] not assigned to an exact location on the device Info: Pin max[26] not assigned to an exact location on the device Info: Pin max[28] not assigned to an exact location on the device Info: Pin max[30] not assigned to an exact location on the device Info: Pin max[32] not assigned to an exact location on the device Info: Pin max[34] not assigned to an exact location on the device Info: Pin max[36] not assigned to an exact location on the device Info: Pin max[38] not assigned to an exact location on the device Info: Pin max[40] not assigned to an exact location on the device Info: Pin max[42] not assigned to an exact location on the device Info: Pin max[44] not assigned to an exact location on the device Info: Pin max[46] not assigned to an exact location on the device Info: Pin max[48] not assigned to an exact location on the device Info: Pin max[50] not assigned to an exact location on the device Info: Pin QUAN_SIG[0] not assigned to an exact location on the device Info: Pin stat_finish not assigned to an exact location on the device Info: Pin addr_monitor[1] not assigned to an exact location on the device Info: Pin addr_monitor[3] not assigned to an exact location on the device Info: Pin addr_monitor[5] not assigned to an exact location on the device Info: Pin addr_monitor[7] not assigned to an exact location on the device Info: Pin addr_monitor[9] not assigned to an exact location on the device Info: Pin addr_monitor[11] not assigned to an exact location on the device Info: Pin addr_monitor[13] not assigned to an exact location on the device Info: Pin data_out[1] not assigned to an exact location on the device Info: Pin data_out[3] not assigned to an exact location on the device Info: Pin data_out[5] not assigned to an exact location on the device Info: Pin data_out[7] not assigned to an exact location on the device Info: Pin max[1] not assigned to an exact location on the device Info: Pin max[3] not assigned to an exact location on the device Info: Pin max[5] not assigned to an exact location on the device Info: Pin max[7] not assigned to an exact location on the device Info: Pin max[9] not assigned to an exact location on the device Info: Pin max[11] not assigned to an exact location on the device Info: Pin max[13] not assigned to an exact location on the device Info: Pin max[15] not assigned to an exact location on the device Info: Pin max[17] not assigned to an exact location on the device Info: Pin max[19] not assigned to an exact location on the device Info: Pin max[21] not assigned to an exact location on the device Info: Pin max[23] not assigned to an exact location on the device Info: Pin max[25] not assigned to an exact location on the device Info: Pin max[27] not assigned to an exact location on the device Info: Pin max[29] not assigned to an exact location on the device Info: Pin max[31] not assigned to an exact location on the device Info: Pin max[33] not assigned to an exact location on the device Info: Pin max[35] not assigned to an exact location on the device Info: Pin max[37] not assigned to an exact location on the device Info: Pin max[39] not assigned to an exact location on the device Info: Pin max[41] not assigned to an exact location on the device Info: Pin max[43] not assigned to an exact location on the device Info: Pin max[45] not assigned to an exact location on the device Info: Pin max[47] not assigned to an exact location on the device Info: Pin max[49] not assigned to an exact location on the device Info: Pin max[51] not assigned to an exact location on the device Info: Pin QUAN_SIG[1] not assigned to an exact location on the device Critical Warning: From pll_20MHz_inst\|altpll_component\|auto_generated\|pll1\|clk[0] (Rise) to pll_20MHz_inst\|altpll_component\|auto_generated\|pll1\|clk[0] (Rise) (setup and hold) Critical Warning: From pll_20MHz_inst\|altpll_component\|auto_generated\|pll1\|clk[1] (Rise) to pll_20MHz_inst\|altpll_component\|auto_generated\|pll1\|clk[0] (Rise) (setup and hold) Critical Warning: From pll_20MHz_inst\|altpll_component\|auto_generated\|pll1\|clk[0] (Rise) to pll_20MHz_inst\|altpll_component\|auto_generated\|pll1\|clk[1] (Rise) (setup and hold) Critical Warning: The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command. Critical Warning: From pll_20MHz_inst\|altpll_component\|auto_generated\|pll1\|clk[0] (Fall) to pll_20MHz_inst\|altpll_component\|auto_generated\|pll1\|clk[0] (Rise) (setup and hold) Critical Warning: From pll_20MHz_inst\|altpll_component\|auto_generated\|pll1\|clk[1] (Fall) to pll_20MHz_inst\|altpll_component\|auto_generated\|pll1\|clk[0] (Rise) (setup and hold) Critical Warning: From pll_20MHz_inst\|altpll_component\|auto_generated\|pll1\|clk[1] (Rise) to pll_20MHz_inst\|altpll_component\|auto_generated\|pll1\|clk[1] (Rise) (setup and hold) Critical Warning: From pll_20MHz_inst\|altpll_component\|auto_generated\|pll1\|clk[0] (Fall) to pll_20MHz_inst\|altpll_component\|auto_generated\|pll1\|clk[0] (Rise) (setup and hold) Critical Warning: From pll_20MHz_inst\|altpll_component\|auto_generated\|pll1\|clk[1] (Fall) to pll_20MHz_inst\|altpll_component\|auto_generated\|pll1\|clk[0] (Rise) (setup and hold) Critical Warning: From pll_20MHz_inst\|altpll_component\|auto_generated\|pll1\|clk[1] (Rise) to pll_20MHz_inst\|altpll_component\|auto_generated\|pll1\|clk[1] (Rise) (setup and hold) Critical Warning: The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command. Critical Warning: From pll_20MHz_inst\|altpll_component\|auto_generated\|pll1\|clk[0] (Fall) to pll_20MHz_inst\|altpll_component\|auto_generated\|pll1\|clk[0] (Rise) (setup and hold) Critical Warning: From pll_20MHz_inst\|altpll_component\|auto_generated\|pll1\|clk[1] (Fall) to pll_20MHz_inst\|altpll_component\|auto_generated\|pll1\|clk[0] (Rise) (setup and hold) Critical Warning: From pll_20MHz_inst\|altpll_component\|auto_generated\|pll1\|clk[1] (Rise) to pll_20MHz_inst\|altpll_component\|auto_generated\|pll1\|clk[1] (Rise) (setup and hold) Critical Warning: From pll_20MHz_inst\|altpll_component\|auto_generated\|pll1\|clk[0] (Fall) to pll_20MHz_inst\|altpll_component\|auto_generated\|pll1\|clk[0] (Rise) (setup and hold) Critical Warning: From pll_20MHz_inst\|altpll_component\|auto_generated\|pll1\|clk[1] (Fall) to pll_20MHz_inst\|altpll_component\|auto_generated\|pll1\|clk[0] (Rise) (setup and hold) Critical Warning: From pll_20MHz_inst\|altpll_component\|auto_generated\|pll1\|clk[1] (Rise) to pll_20MHz_inst\|altpll_component\|auto_generated\|pll1\|clk[1] (Rise) (setup and hold) Critical Warning: The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command. Critical Warning: From pll_20MHz_inst\|altpll_component\|auto_generated\|pll1\|clk[0] (Fall) to pll_20MHz_inst\|altpll_component\|auto_generated\|pll1\|clk[0] (Rise) (setup and hold) Critical Warning: From pll_20MHz_inst\|altpll_component\|auto_generated\|pll1\|clk[1] (Fall) to pll_20MHz_inst\|altpll_component\|auto_generated\|pll1\|clk[0] (Rise) (setup and hold) Critical Warning: From pll_20MHz_inst\|altpll_component\|auto_generated\|pll1\|clk[1] (Rise) to pll_20MHz_inst\|altpll_component\|auto_generated\|pll1\|clk[1] (Rise) (setup and hold) Critical Warning: From pll_20MHz_inst\|altpll_component\|auto_generated\|pll1\|clk[0] (Fall) to pll_20MHz_inst\|altpll_component\|auto_generated\|pll1\|clk[0] (Rise) (setup and hold) Critical Warning: From pll_20MHz_inst\|altpll_component\|auto_generated\|pll1\|clk[1] (Fall) to pll_20MHz_inst\|altpll_component\|auto_generated\|pll1\|clk[0] (Rise) (setup and hold) Critical Warning: From pll_20MHz_inst\|altpll_component\|auto_generated\|pll1\|clk[1] (Rise) to pll_20MHz_inst\|altpll_component\|auto_generated\|pll1\|clk[1] (Rise) (setup and hold) Critical Warning: Timing requirements not met 0 4.png (16.56 KB, 下载次数: 3) 3.png (19.06 KB, 下载次数: 3) 2.png (20.44 KB, 下载次数: 3) 1.png (23.77 KB, 下载次数: 3)
2020-4-29 16:23:29　　评论淘帖0 邀请回答您可以邀请以下用户，快速回答问题 × 刘英该类别下有 31 个回答。邀请回答 chenbingjy 该类别下有 27 个回答。邀请回答 yoonssica 该类别下有 22 个回答。邀请回答 houxiaoxiao 该类别下有 17 个回答。邀请回答小萃米该类别下有 16 个回答。邀请回答小工兵该类别下有 16 个回答。邀请回答 Elecfans管家该类别下有 15 个回答。邀请回答薄迪该类别下有 14 个回答。邀请回答我爱妖妖该类别下有 14 个回答。邀请回答言尽于此33 该类别下有 14 个回答。邀请回答 hxing 该类别下有 13 个回答。邀请回答那些年儿ing 该类别下有 13 个回答。邀请回答平漂流该类别下有 13 个回答。邀请回答 xiekaboy 该类别下有 12 个回答。邀请回答 1653344032.827400 该类别下有 12 个回答。邀请回答小麦地该类别下有 12 个回答。邀请回答科比如我该类别下有 12 个回答。邀请回答倪love 该类别下有 12 个回答。邀请回答英雄孤寂该类别下有 11 个回答。邀请回答黄月明该类别下有 11 个回答。邀请回答举报马守川相关推荐 • FPGA实战演练逻辑篇56：VGA驱动接口时序设计之3时钟约束 5478 • 如何在FPGA设计环境中加入时序约束？ 1771 • 关于时序约束，该怎么开始？ 10872 • FPGA实战演练逻辑篇61：CMOS摄像头接口时序设计1理想时序 4542 • .UCF计时时序约束中只指定对300MHz信号约束 2670 • 时序警告，新手求问约束的问题 4109 • 咨询关于timequest中launch edge和latch edge相同的问题 5807 • Spartan-3 DCM需要哪些时序分析约束？ 1482 • FPGA实战演练逻辑篇59：VGA驱动接口时序设计之6建立和保持时间约束 3569 • FPGA实战演练逻辑篇48：基本的时序分析理论1 5241 1个回答

答案对人有帮助，有参考价值 0 01.引脚分配未完成，由此导致严重警告。 02.理论上讲，程序可以加载并运行（掩耳盗铃的方式，忽略警告）。 03.对于时序不满足要求的情况，建议尝试一下如下方式：即针对相位进行微调，调整数值和你设置的频率相关。 04.还有一种正规方式，分析时序报告，查看哪里不符合设计规范进行更改，如果还有警告，在.sdc中加入时序优化指令（不是忽略指令）。这一点我不太会。 Quartus-II_PLL_set.png (99.72 KB, 下载次数: 3)*

2020-4-29 17:56:54 评论举报卿小小_9e6