McBSP采用EDMA3方式进行数据采集一次中断都不进入是怎么回事

[tr]McBSP与aic23相连，AIC23为主模式，单独验证了只使用McBSP单个数据采集与发送，可以正常将输入信号输出。然后将StarterWare中的Audio_Line_In例程中的McASP改为McBSP。程序运行后，EDMA3中断一次都不进入，查看McBSP的DRR有接收数据，DXR没有发送数据。以下为McBSP的设置，请教，在将例程中的McASP的相应地方改为McBSP之外，还有哪些地方需要改动？McBSP需要开FIFO吗？
void McBSP0Init(void)
{
    // McBSP0 串行口控制寄存器
    McBSP0Regs.SPCR.bit.FREE = MCBSP_SPCR_FREE_NO;//Free-running mode enable, during emulation halt, serial clocks continue to run.
    McBSP0Regs.SPCR.bit.SOFT = MCBSP_SPCR_SOFT_NO;//soft mode enable,this bit has no effect if FREE=1
    McBSP0Regs.SPCR.bit.DLB = MCBSP_SPCR_DLB_OFF;// DLB    = 0,禁止自闭环方式
    McBSP0Regs.SPCR.bit.RJUST = MCBSP_SPCR_RJUST_LZF;//left justify the data and zero fill LSBS
    McBSP0Regs.SPCR.bit.CLKSTP = MCBSP_SPCR_CLKSTP_DISABLE;//Clock stop mode disable
    McBSP0Regs.SPCR.bit.DXENA = MCBSP_SPCR_DXENA_ON;
    McBSP0Regs.SPCR.bit.RINTM = MCBSP_SPCR_RINTM_RRDY;//sends a receive INT request to CPU when the RRDY bit
    McBSP0Regs.SPCR.bit.XINTM = MCBSP_SPCR_XINTM_XRDY;//transmit interrupt mode bits XRDY bit changes from 0 to1
    // 禁用 FRST GRST XRST RRST
    McBSP0Regs.SPCR.bit.FRST = MCBSP_SPCR_FRST_RESET;//frame-sync generator reset bit, frame-sync signal(FSG) is not generated by the sample-rate generator.
    McBSP0Regs.SPCR.bit.GRST = MCBSP_SPCR_GRST_RESET;//sample-rate generator reset
    McBSP0Regs.SPCR.bit.XRST = MCBSP_SPCR_XRST_DISABLE;//serial port transmitter is disabled and in reset state
    McBSP0Regs.SPCR.bit.RRST = MCBSP_SPCR_RRST_DISABLE;//serial port receiver is disabled and in reset state

    // McBSP0 管脚控制寄存器
    // 发送帧同步信号由外部输入
    McBSP0Regs.PCR.bit.FSXM = MCBSP_PCR_FSXM_EXTERNAL;//transmit frame-synchronization signal is derived from external source, FSX is an input pin.
    // 接收帧同步信号由外部输入
    McBSP0Regs.PCR.bit.FSRM = MCBSP_PCR_FSRM_EXTERNAL;//receive frame-synchronization signal is derived from an external source, FSR is an input pin.
    // 发送时钟信号由外部输入
    McBSP0Regs.PCR.bit.CLKXM = MCBSP_PCR_CLKXM_INPUT;//CLKX is an input pin and is driven by an external clock
    // 接收时钟信号由外部输入
    McBSP0Regs.PCR.bit.CLKRM = MCBSP_PCR_CLKRM_INPUT;//receive clock-CLKR is an output pin and is driven by the internal sample-rate generator
    // 内部采样率生成器时钟信号由 McBSP 内部输入时钟产生(DSP 时钟频率 1/2)
    McBSP0Regs.PCR.bit.SCLKME = MCBSP_PCR_SCLKME_NO;//sample rate generator input clock mode bit, conjunction with CLKSM bit to select the input clock,McBSP internal input clock
    // 发送帧同步信号高电平有效
    McBSP0Regs.PCR.bit.FSXP = MCBSP_PCR_FSXP_ACTIVEHIGH;//transmit frame-synchronization polarity bit: active high
    // 接收帧同步信号高电平有效
    McBSP0Regs.PCR.bit.FSRP = MCBSP_PCR_FSRP_ACTIVEHIGH;//receive frame-synchronization pulse is active high
    // 发送数据在时钟信号下降沿采样
    McBSP0Regs.PCR.bit.CLKXP = MCBSP_PCR_CLKXP_FALLING;//transmit data driven on falling edge of CLKX
    // 接收数据在时钟信号上升沿采样
    McBSP0Regs.PCR.bit.CLKRP = MCBSP_PCR_CLKRP_FALLING;//receive data sampled on edge rising of CLKR

    // McBSP0 接收控制寄存器
    // 单数据相，接收数据长度为16位,每相2个数据
    McBSP0Regs.RCR.bit.RPHASE = MCBSP_RCR_RPHASE_SINGLE;//dual-phase frame
    // 指定相位 2 接收帧长度(2个字)
    McBSP0Regs.RCR.bit.RFRLEN2 = MCBSP_RCR_RFRLEN2_OF(1);//2 words in phase
    // 指定相位 2 接收字长度(16 位)
    McBSP0Regs.RCR.bit.RWDLEN2 = MCBSP_RCR_RWDLEN2_16BIT;//receive word length is 16 bits
    // 无压缩 MSB(最高有效位)
    McBSP0Regs.RCR.bit.RCOMPAND = MCBSP_RCR_RCOMPAND_MSB;//no companding, data transfer starts with MSB first
    // 第一个帧脉冲重新开始传输之后，接收帧同步脉冲
    McBSP0Regs.RCR.bit.RFIG = MCBSP_RCR_RFIG_YES;//Receive frame-sync ignore bit, 1, frame-sync detect
    // 接收数据延迟位
    McBSP0Regs.RCR.bit.RDATDLY = MCBSP_RCR_RDATDLY_1BIT;//Receive data delay bits, 1-bit data delay
    // 指定相位 1 接收帧长度(2 个字)
    McBSP0Regs.RCR.bit.RFRLEN1 = MCBSP_RCR_RFRLEN1_OF(1);//receive frame length in phase1:2 words
    // 指定相位1 接收字长度(16 位)
    McBSP0Regs.RCR.bit.RWDLEN1 = MCBSP_RCR_RWDLEN1_32BIT;//receive word length in phase1: 16 bits
    // 无数据位倒置
    McBSP0Regs.RCR.bit.RWDREVRS = MCBSP_RCR_RWDREVRS_NO;//receive 32-bit bit reversal disable

    // McBSP0 发送控制寄存器
    // 单相位帧，发送数据长度为16位，每相2个数据
    McBSP0Regs.XCR.bit.XPHASE = MCBSP_XCR_XPHASE_SINGLE;//transmit phase bit: dual-phase frame
    // 指定相位 2 发送帧长度(2个字)
    McBSP0Regs.XCR.bit.XFRLEN2 = MCBSP_XCR_XFRLEN2_OF(1);//transmit frame length in phase2: 2 words
    // 指定相位 2 发送字长度(16 位)
    McBSP0Regs.XCR.bit.XWDLEN2 = MCBSP_XCR_XWDLEN2_16BIT;//transmit word length in phase2: 16 bits
    // 无压缩 MSB(最高有效位)
    McBSP0Regs.XCR.bit.XCOMPAND = MCBSP_XCR_XCOMPAND_MSB;//transmit no companding, data transfer starts with MSB first
    // 第一个帧脉冲重新开始传输之后，发送帧同步脉冲
    McBSP0Regs.XCR.bit.XFIG = MCBSP_XCR_XFIG_YES;//Transmit frame-sync ignore bit, 1, frame-sync detect
    // 发送数据延迟位
    McBSP0Regs.XCR.bit.XDATDLY = MCBSP_XCR_XDATDLY_1BIT;//transmit data delay bit: 1-bit
    // 指定相位 1 发送帧长度(2 个字)
    McBSP0Regs.XCR.bit.XFRLEN1 = MCBSP_XCR_XFRLEN1_OF(1);//transmit frame length in phase1: 2 words
    // 指定相位 1 发送字长度(16 位)
    McBSP0Regs.XCR.bit.XWDLEN1 = MCBSP_XCR_XWDLEN1_32BIT;//transmit word length in phase1: 16 bits
    // 无数据位倒置
    McBSP0Regs.XCR.bit.XWDREVRS = MCBSP_XCR_RWDREVRS_NO;//transmit 32-bit reversal feature disable

    // 延时等待内部同步
    unsigned char i;
    for(i=0;i<100;i++)
        asm (" nop");

    // 使能 接收
   // McBSP0Regs.SPCR.bit.RRST = MCBSP_SPCR_RRST_ENABLE;//serial port receiver is enabled
    // 使能 发送
    //McBSP0Regs.SPCR.bit.XRST = MCBSP_SPCR_XRST_ENABLE;//serial port transmitter is enabled

    for(i=0;i<100;i++)
        asm (" nop ");
}

使能McBSP的接收与发射是放在使能EDMA3传输之后。请赐教！

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