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我工作在一个项目的措施,从太阳辐射传感器输出的模拟。我是新手,对ADC的各种设置的一些困惑。看来,根据缓冲区模式,我得到了完全不同的解读,甚至当增益设置为1。绕过缓冲似乎为我提供最合理的解读,但仍不准确。用电压表测量值,我在1500微伏,但ADC吐阅读只有约600微伏。改变转换模式没有任何区别的读数,滴当然采样速率减慢更新间隔。
有谁遇到这样的问题的时候,试图在低振幅使用∑-ΔADC?的adcworks就好当我连接引脚的外部电压源,要大得多(而不是小于毫伏电压1.5V),但我认为ADC可能有问题由于我测量我附上我的配置和我的采样编码的低幅度的屏幕截图下面,虽然它不是来自造物主的样本项目非常不同 AdcDelsiGyStiX(); ADCJ-DESIGIL选择配置(ADCJ-DESIGIGCFG1,1); AdcDeligySistCurror(); CyDelay(100U); (i=0;i,lt;100;i++) { 如果(ADCJ-DESIGION ISEDATION转换(ADCJ-DeligiaWaITyFuri结果)) { 输出= adc_delsig_countsto_uvolts(adc_delsig_getresult32()); 断裂; } CyDelay(5U); } AdcDeligyStoCurror(); ADC组态 38.4 K 以上来自于百度翻译 以下为原文 I am working on a project that measures an analog output from a solar radiation sensor. I am a novice and have some confusion about the various settings for the Delta Sigma ADC. It seems that, depending on the buffer mode, I get wildly different readings, even when the gain is set to 1. Bypassing the buffer seems to provide me with the most reasonable readings, but still not accurate. Using a voltmeter, I measure values of around 1500 microvolts, yet the ADC spits out a reading of only about 600 microvolts. Changing the conversion mode didn't make any difference to the readings, and dropping the sampling rate of course only slowed down the update interval. Has anyone run into issues like this before when trying to use the delta sigma ADC at low amplitudes? The ADC works just fine when I connect the pins to an external voltage source that is much greater (1.5V instead of less than a millivolt), but I think the ADC may be having issues due to the low magnitude of what I'm measuring I've attached a screen shot of my configuration and my sampling code is below, though it's not much different from the sample project on creator ADC_DelSig_Start(); ADC_DelSig_SelectConfiguration(ADC_DelSig_CFG1,1); ADC_DelSig_StartConvert(); CyDelay(100u); for(i = 0; i < 100; i++) { if(ADC_DelSig_IsEndConversion(ADC_DelSig_WAIT_FOR_RESULT)) { output = ADC_DelSig_CountsTo_uVolts(ADC_DelSig_GetResult32()); break; } CyDelay(5u); } ADC_DelSig_StopConvert();
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HTTP://www. CyPress?COM/?摆脱= 39677 an57821 - PSoC®三,PSoC,5lp和PSoC混合信号电路板布局的思考 HTTP://www. CyPress?COM/?摆脱= 43337 an61290 - PSoC®三和PSoC 5lp硬件设计注意事项 HTTP://www. CyPress?COM/?= 40247 an58827摆脱PSoC 3和PSoC 5lp -®内部模拟布线的考虑 hli指出,在配置工具厘米范围图形外观。如果你绕过缓冲你就会超过真正的R-R性能。 问候,Dana。 以上来自于百度翻译 以下为原文 This might help - http://www.cypress.com/?rID=39677 AN57821 - PSoC® 3, PSoC 4, and PSoC 5LP Mixed Signal Circuit Board Layout Considerations http://www.cypress.com/?rID=43337 AN61290 - PSoC® 3 and PSoC 5LP Hardware Design Considerations http://www.cypress.com/?rID=40247 AN58827 - PSoC® 3 and PSoC 5LP Internal Analog Routing Considerations As hli points out look at graphic of CM range in config tool. If you bypass the buffer you will get/exceed true R-R performance. Regards, Dana. |
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如果你阅读了AP笔记也绕过了VREF。
附加一些旧的但非常适用的AP信号路径注释 错误及其处理。 这是你自己的布局还是使用CyPress DVK? 问候,Dana。 所有ATOD错误11Zip 12.1兆字节 以上来自于百度翻译 以下为原文 If you read the ap notes bypassing Vref importent as well. Attached some old but very applicable ap notes on signal path errors and dealing with them. Is this your own layout or you using a Cypress DVK ? Regards, Dana.
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