请问有什么好办法能从这个FPGA读取13位ADC的数值？

嗨，
我正在使用Spartan 6“xc6slx9-2tqg144”并使用VHDL中的ISE Project Navigator 14.3进行编程。
我正在研究的项目涉及一个ADC，用于从带有FPGA的超声波收发器收集数值，并将一组这些值传输到计算机。
该ADC具有13位分辨率（差分输入），与FPGA一样，由200MHz时钟驱动。
我把ADC包括在内：
图书馆IEEE;
使用IEEE.STD_LOGIC_1164.ALL;
使用IEEE.NUMERIC_STD.ALL;
图书馆UNISIM;
使用UNISIM.VComponents.all;
实体ADCis
端口（ADC_Data＆amp;冒号;在STD_LOGIC_VECTOR（12 downto 0）; ADC_Data_N：在STD_LOGIC_VECTOR（12 downto 0））;
结束ADC;
建筑行为的ADCis
....
signal ADC_int：integer：= 0; signal ADC_Data_IBUFDS_out：STD_LOGIC_VECTOR（12 downto 0）;
...
开始
ADC_Data_IBUFDS_0：unisim.vcomponents.IBUFDS端口映射（I => ADC_Data（0），IB => ADC_Data_N（0），O => ADC_Data_IBUFDS_out（0））;
...
（重复1-11）
...
ADC_Data_IBUFDS_12：unisim.vcomponents.IBUFDS端口映射（I => ADC_Data（12），IB => ADC_Data_N（12），O => ADC_Data_IBUFDS_out（12））;
ADC_int
endBehavioral;
输入引脚在ucf文件中定义如下：
NET“ADC_Data [0]”LOC = P140 |
IOSTANDARD = LVDS_25; NET“ADC_Data [1]”LOC = P142 |
IOSTANDARD = LVDS_25; NET“ADC_Data [2]”LOC = P2 |
IOSTANDARD = LVDS_25; NET“ADC_Data [3]”LOC = P6 |
IOSTANDARD = LVDS_25; NET“ADC_Data [4]”LOC = P8 |
IOSTANDARD = LVDS_25; NET“ADC_Data [5]”LOC = P10 |
IOSTANDARD = LVDS_25; NET“ADC_Data [6]”LOC = P12 |
IOSTANDARD = LVDS_25; NET“ADC_Data [7]”LOC = P15 |
IOSTANDARD = LVDS_25; NET“ADC_Data [8]”LOC = P17 |
IOSTANDARD = LVDS_25; NET“ADC_Data [9]”LOC = P22 |
IOSTANDARD = LVDS_25; NET“ADC_Data [10]”LOC = P24 |
IOSTANDARD = LVDS_25; NET“ADC_Data [11]”LOC = P27 |
IOSTANDARD = LVDS_25; NET“ADC_Data [12]”LOC = P30 |
IOSTANDARD = LVDS_25;
这些端口在UG385中描述为相应差分引脚对的正引脚。
这种配置似乎有效，因为我从ADC获得实际的实际值。
但它似乎打扰了并行运行的其他进程。
我还通过串行连接将一组数字值传输到我的PC（当然速度慢得多（100kHz）），并且在一些成功的传输后我得到了帧错误。
当我评论ADC部件时，我的串行传输完美地与静态或递增值而不是ADC值一起工作。
我做了一些根本错误的事情，还是有更好的方法从这个FPGA读取13位ADC的数值？



以下为原文

Hi,
I'm using a Spartan 6 "xc6slx9-2tqg144" and programming it with ISE Project Navigator 14.3 in VHDL.
The project i'm working on involves an ADC to gather numerical values from an ultrasonic transceiver with a FPGA and transmit a set of these values to a computer. This ADC has a 13bit resolution (differential input) and is driven by a 200MHz clock just like the FPGA.

I included the ADC like this:


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library UNISIM;
use UNISIM.VComponents.all;

entity ADC is
Port ( ADC_Data : in STD_LOGIC_VECTOR(12 downto 0);
          ADC_Data_N : in STD_LOGIC_VECTOR(12 downto 0) );

end ADC;

architecture Behavioral of ADC is
....
signal ADC_int : integer:=0;
signal ADC_Data_IBUFDS_out : STD_LOGIC_VECTOR (12 downto 0);
...
begin

ADC_Data_IBUFDS_0: unisim.vcomponents.IBUFDS
port map (
I => ADC_Data(0),
IB => ADC_Data_N(0),
O => ADC_Data_IBUFDS_out(0)
);


...
(repeat for 1-11)
...

ADC_Data_IBUFDS_12: unisim.vcomponents.IBUFDS
port map (
I => ADC_Data(12),
IB => ADC_Data_N(12),
O => ADC_Data_IBUFDS_out(12)
);


ADC_int <= to_integer(unsigned(ADC_Data_IBUFDS_out));

end Behavioral;


The input-pins are defined in the ucf-file like this:
NET "ADC_Data[0]" LOC = P140 | IOSTANDARD = LVDS_25;
NET "ADC_Data[1]" LOC = P142 | IOSTANDARD = LVDS_25;
NET "ADC_Data[2]" LOC = P2 | IOSTANDARD = LVDS_25;
NET "ADC_Data[3]" LOC = P6 | IOSTANDARD = LVDS_25;
NET "ADC_Data[4]" LOC = P8 | IOSTANDARD = LVDS_25;
NET "ADC_Data[5]" LOC = P10 | IOSTANDARD = LVDS_25;
NET "ADC_Data[6]" LOC = P12 | IOSTANDARD = LVDS_25;
NET "ADC_Data[7]" LOC = P15 | IOSTANDARD = LVDS_25;
NET "ADC_Data[8]" LOC = P17 | IOSTANDARD = LVDS_25;
NET "ADC_Data[9]" LOC = P22 | IOSTANDARD = LVDS_25;
NET "ADC_Data[10]" LOC = P24 | IOSTANDARD = LVDS_25;
NET "ADC_Data[11]" LOC = P27 | IOSTANDARD = LVDS_25;
NET "ADC_Data[12]" LOC = P30 | IOSTANDARD = LVDS_25;


These ports are described in the UG385 as positive pins of a corresponding differential-pin pair.

This configuration seems to work as i get actual realistic values from the ADC. But it seems to disturb other processes running parallel. I also transfer a set of nummerical values via serial connection to my PC (at a much slower clock rate of course (100kHz)) and just after some successful transmissions i get framing errors. When i comment the ADC parts my serial transmission works perfectly with static or incrementing values instead of the ADC values.

Did I do something fundamentally wrong or is there a better way to read nummerical values from a 13bit ADC with this FPGA?