使用时钟生成AFE控制信号这个主意好吗？

不，这不是一个好主意。
从专用时钟网到门的路由几乎不可能受到限制。
您想要做什么（生成1/2时钟周期输出脉冲）可以使用ODDR原语完成。
有关您正在使用的技术，请参阅“SelectIO资源用户指南”中的单元格说明
不使用AND门，而是使用ODDR。
ODDR在CLK的上升沿驱动D1输入，在下降沿驱动D2，所以为了做你想做的事，你可以使用现有的计数器。
您希望时钟前半部分（上升沿之后）的数据为0，因此将D1连接到0.在时钟的后半部分（下降沿之后），您希望输出仅在1时为1
s_comp被断言，因此将其用作D2输入。
当然，ODDR只能直接连接到输出缓冲器，但这就是我想要做的事情（因为在FPGA内部有一个半时钟周期信号是没有意义的。
Avrum
在原帖中查看解决方案



以下为原文

No, this is not a good idea. The routing from the dedicated clock net through the gate will be nearly impossible to constrain.
 
What you want to do (generate a 1/2 clock period output pulse) can be done with an ODDR primitive. See the description of the cell in the SelectIO Resources User Guide for the technology that you are using
 
Instead of using the AND gate, use the ODDR.
 
The ODDR drives the D1 input to the output on the rising edge of CLK and the D2 on the falling edge, so to do what you want, you can use your existing counter. You want the data during the first half of the clock (after the rising edge) to be 0, so tie D1 to 0. During the second half of the clock (after the falling edge), you want the output to be 1 only when s_comp is asserted, so use this as the D2 input.
 
Of course, the ODDR can only be connected directly to an output buffer, but that is what I assume you want to do (since it doesn't make sense to have a half clock period signal inside the FPGA.
 
Avrum
View solution in original post

只是一个纠正：
S_OUT



以下为原文

Just a correction:
s_out <= not clk when (s_comp = '1') else '0';process(clk) beginif rising_edge(clk) thenif s_count = 5 thens_count <= 0;s_comp <= '1';   -- Editelses_count <= s_count + 1;s_comp <= '0';end if;end if;end process; 

不，这不是一个好主意。
从专用时钟网到门的路由几乎不可能受到限制。
您想要做什么（生成1/2时钟周期输出脉冲）可以使用ODDR原语完成。
有关您正在使用的技术，请参阅“SelectIO资源用户指南”中的单元格说明
不使用AND门，而是使用ODDR。
ODDR在CLK的上升沿驱动D1输入，在下降沿驱动D2，所以为了做你想做的事，你可以使用现有的计数器。
您希望时钟前半部分（上升沿之后）的数据为0，因此将D1连接到0.在时钟的后半部分（下降沿之后），您希望输出仅在1时为1
s_comp被断言，因此将其用作D2输入。
当然，ODDR只能直接连接到输出缓冲器，但这就是我想要做的事情（因为在FPGA内部有一个半时钟周期信号是没有意义的。
Avrum



以下为原文

No, this is not a good idea. The routing from the dedicated clock net through the gate will be nearly impossible to constrain.
 
What you want to do (generate a 1/2 clock period output pulse) can be done with an ODDR primitive. See the description of the cell in the SelectIO Resources User Guide for the technology that you are using
 
Instead of using the AND gate, use the ODDR.
 
The ODDR drives the D1 input to the output on the rising edge of CLK and the D2 on the falling edge, so to do what you want, you can use your existing counter. You want the data during the first half of the clock (after the rising edge) to be 0, so tie D1 to 0. During the second half of the clock (after the falling edge), you want the output to be 1 only when s_comp is asserted, so use this as the D2 input.
 
Of course, the ODDR can only be connected directly to an output buffer, but that is what I assume you want to do (since it doesn't make sense to have a half clock period signal inside the FPGA.
 
Avrum

非常感谢avrumw，这正是我想要做的！
我想过使用ODDR，但之前并没有那么清楚。
现在它是...
干杯，
croto



以下为原文

Thank you so much avrumw, that is exactly what I want to do!
I thought about using the ODDR, but it wasn't that clear before. Now it is...
 
Cheers,
croto