为什么TIG1需要在356和3144之间以获得每个PWM周期的触发？

我正试图了解ADC触发从PWM到ADC的工作原理。这是我迄今为止得到的：PWM设置：ADC设置：为什么tiG1需要在356和3144之间以获得每个PWM周期的触发？在上面或下面，它每2个周期移动到1个触发点。我在DSSPIC33 EP128MC204MPLABX 3.35Win 7XC16V1.26上进行测试。



      以下为原文

    I'm trying to learn how the ADC triggering works from pwm to adc.  Here's what I've got so far:

PWM Setup:
  //Timing
    PTCON = 0; //pwm module disabled
    PTCON2 = 0; // Divide by 1 to generate PWM
    PHASE1 = (FCY/FPWM - 1); //FCY = 70000000, FPWM = 20000
    PHASE2 = (FCY/FPWM - 1);
    PHASE3 = (FCY/FPWM - 1);
    PDC1 = PHASE1 / 2;
    PDC2 = PHASE1 / 2;
    PDC3 = PHASE1 / 2; // Initialize as 0 voltage
   
    //PWM Gen Control
    PWMCON1 = 0; //default
    PWMCON1bits.CAM = 1; //center aligned
    PWMCON1bits.ITB = 1; //PHASEx provides time base for this pwm generator
    PWMCON1bits.MDCS = 0; //PDCx register provides duty for this generator
    PWMCON2 = PWMCON1; //see above
    PWMCON3 = PWMCON1; //see above
    PWMCON1bits.TRGIEN = 1; //this triggers the PWM1 Interrupt (Not other peripherals)
   
    //IO Control
    IOCON1 = 0; //default
    IOCON1bits.PENH = 1; //pwm h controlled by pwm module
    IOCON1bits.PENL = 1; //pwm l controlled by pwm module
    IOCON1bits.POLH = 0; //pin active high
    IOCON1bits.POLL = 0; //pin active high
    IOCON1bits.PMOD = 0; //complementary mode
    IOCON1bits.OVRENH = 0; //not overridden by OVERDAT
    IOCON1bits.OVRENL = 0; //not overriddden by OVERDAT
    IOCON2 = IOCON1; //see above
    IOCON3 = IOCON1; //see above
   
    //Dead time control
    DTR1 = 0; //not used in this mode
    DTR2 = DTR1; //not used in this mode
    DTR3 = DTR3; //not used in this mode
    ALTDTR1 = ALTDTR_DIV2 << 1;  //ALTDTR_DIV2 = 150
    ALTDTR2 = ALTDTR1;
    ALTDTR3 = ALTDTR1;
   
    //Trigger
    TRIG1 = 355; //If I set this to 356 it works, 355 or lower and it does not
    TRGCON1bits.TRGDIV = 0; //trigger on every match event
    TRGCON1bits.TRGSTRT = 0; //trigger on first match event
   
    //Fault control
    FCLCON1 = 0; //default
    FCLCON1bits.FLTMOD = 3; //Fault input is disabled
    FCLCON1bits.CLMOD = 0; //Current limit mode is disabled
    FCLCON2 = FCLCON1; //see above
    FCLCON3 = FCLCON1; //see above
   
    //Run
    PTCONbits.PTEN = 1; //enable pwm
ADC Setup:
     //Analog Channels:

    ANSELA = 3;

    ANSELB = 3;

    ANSELC = 4;
    AD1CON1 = 0;
    AD1CON1bits.ASAM = 1; //auto start sampling
    AD1CON1bits.FORM = 3; //Signed Fractional
    AD1CON1bits.SIMSAM = 1; //simultaneous sampling (10b only)
    AD1CON1bits.SSRCG = 1; //SSRC Selection Group: 0,1,2: PWM[1,2,3] Prim Trig, 3,4,5,6: PTGO[12,13,14,15] Primary Trigger]
    AD1CON2 = 0;
    AD1CON2bits.CHPS = 2; //convert CH0,CH1, CH2, CH3
    AD1CON2bits.SMPI = 1; //generate interrupt after 4th conversion
    AD1CON2bits.ALTS = 1; //use channel input select for sample MUXA on first Sample, MUXB on next Sample
/* Set Samples and bit conversion time */
    AD1CON3 = 0;
    AD1CON3bits.SAMC = 3; //Auto Sample Time = 3 Tad
    AD1CON3bits.ADCS = 6; //7*Tp = Tad (NOT USED)
    AD1CSSH = 0;
    AD1CSSL = 0;
    AD1CSSLbits.CSS3 = 1;
    AD1CSSLbits.CSS8 = 1;
    AD1CHS0bits.CH0SA = 3; //AN3 connected to Channel 0 MUXA
    IFS0bits.AD1IF = 0; //reset interrupt flag
    IEC0bits.AD1IE = 1; //enable interrupt
    AD1CON1bits.ADON = 1; //turn on ADC module

Why does TRIG1 need to be between 356 and 3144 to get a trigger every pwm period?  Above or below that it moves to 1 trigger every 2 periods.

I am testing this on a dspic33ep128mc204
MPLABX 3.35
Win 7
XC16v1.26