为什么设计可以依赖斯巴达6编译？

假设没有时间/编码错误=>
为什么设计可以依赖于编译？
- 如果没有警告（没有锁存器，没有未定义的状态，功能和时序仿真工作）
- 如果Planahead 14,6标准和跟踪报告后没有计时错误。
（所有时钟的时序都放宽了0.5 ns）
- 如果输出信号被约束覆盖。
我正在使用我编辑的Xilinx反序列化模板，并且块上没有编码错误。
我实例化相同的反序列化块9次，它只在2个数据通道％25的编译中失败。
FPGA在一些编译中的表现令人难以置信。
当它工作时，它总能正常工作，即使我将FPGA 70度或在几秒钟内冻结到10度。
你建议在一个固定的位置锁定反序列化块吗？
我听说赛灵思提出了这个建议，并说这是因为Spartan 6不是PVT压缩甚至使用了相位检测。



以下为原文

Assuming that there are no timing/coding mistakes =>
How come a design can be compilation dependent?

• - If there are no warnings(no latches, no undefined states, func and timing simulation works)
• - if there are no timing errors after Planahead 14,6 par and trace report. (Timing is relaxed by 0.5 ns in all clocks)
• - if output signals are covered by constraints.
  

I am using a Xilinx deserialization template that I edited and there are no coding mistakes on the block.
I instantiate the same deserialization block 9 times and it fails only in 2 data channels %25 of the compilations.

The FPGA performs unbeliably well in some compilations.
When it works, it always works correctly even I make the FPGA 70 degrees or freeze it to 10 degrees in few seconds.

Do you suggest to lock deserialization block on a fixed location?
I heard that Xilinx suggest this and says it is because Spartan 6 is not PVT compansated even phase detection used.