PSoC5LP设备占空比随写入频率而变化

嗨，我是新的PSoC编程，我遇到了一些令人困惑的行为。我有一个PSoC5LP设备，我正在尝试使用设备上的端口开发一个并行接口。我通过在端口上写两个交替值开始测试我的写入速度：具体来说，我把0x40和0x01写入了p6的正确寄存器。这些值将交替驱动P6Y6高和P6Y0高。也就是说，虽然P6Y6是高的，P6Y0是低的，反之亦然。如果我以一个相当慢的速度，我得到一个不错的波形，你会期望从这些引脚，奇怪的是，每当我试图优化总线速度和时钟速度，以达到总的频率超过2MHz的某处，我得到一个有点变形的占空比在两个引脚。因此，在我之前在两个引脚上有大约50%个占空比之前，现在我在一个引脚上有大约33%的占空比，另一个上有66%的占空比。以下是慢速和高速下波形的一些图像：



     以下为原文
  Hi, I am new to PSoC programming, and I have encountered some confusing
behavior. I have a PSoC5 LP device, and I'm trying to develop a parallel
interface using a port on the device. I began testing my write speed by simply
writing two alternating values on the port: specifically, I wrote 0x40 and 0x01
to the correct register for P6. These values will alternate driving P6_6 high
and P6_0 high. That is, while P6_6 is high, P6_0 is low, and vice versa. If I do
this at a rather slow speed, I get a nice waveform that you'd expect from these
pins, What is strange is that whenever I try to optimize the bus speed and clock
speed to achieve an overall frequency somewhere above ~2MHz, I get a somewhat
deformed duty cycle on both pins. So where before I'd have about a 50% duty
cycle on both pins, now I have about a 33% duty cycle on one pin, and a 66% duty
cycle on the other. Here are some images of the waveforms at the slow and high
speeds, respectively: