请问在Spartan 6上浮动时差异输入的行为是什么？

如果差分接收器引脚的逻辑状态在未被驱动时不重要（例如，如果输入寄存器已禁用），则无需执行任何操作。
如果存在足够的噪声，接收器的输出可能会切换;
但是，这不会损坏设备。
切换可能会导致设备内的功耗和噪声增加;
然而，这些将是相当微不足道的。如果有必要将接收器的引脚保持在已知的逻辑状态，输入可以通过上拉至VCCO进行直流偏置，并下拉至GND。设计目标是获得
输入差分电压达到确保已知逻辑电平处于IBUFDS输出的电平，同时仍确保输入引脚的信号完整性良好。
您应选择上拉和下拉电阻，以便在未驱动的情况下，差分输入电压大于数据手册中差分输入标准的最小VID。
然后，您应该执行IBIS或Spice仿真，输入以所需的工作频率驱动，以确保仍满足输入规范，并确保输入端具有良好的信号完整性。
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以下为原文

If the logical state of the differential receiver's pins is not important when they left un-driven (e.g., if input registers have been disabled), you do not need to do anything. The receiver's output might toggle if enough noise is present; however, this will not damage the device. The toggling might lead to increased power consumption and noise within the device; however, these will be fairly insignificant.

If it is necessary to keep the receiver's pins at a known logical state, the inputs can be DC-biased with a pull-up to VCCO and pull-down to GND.
The design goal is to get the input differential voltage to a level that ensure a known logic level is at the IBUFDS output while still ensuring that the signal integrity is good at the input pin.

You should select the Pull-up and Pulldown resistors such that in the undriven case the differential input voltage is greater than minimum VID for the differential input standard in the data sheet.

You should then perform an IBIS or Spice simulation with the input being driven at the desired operating frequency to ensure that the input specifications are still met and that there is good signal integrity at the input.-----------------------------------------------------------------------------------------------
Please mark the post as "Accept as solution" if the information provided answers your query/resolves your issue.

Give Kudos to a post which you think is helpful.View solution in original post

如果差分接收器引脚的逻辑状态在未被驱动时不重要（例如，如果输入寄存器已禁用），则无需执行任何操作。
如果存在足够的噪声，接收器的输出可能会切换;
但是，这不会损坏设备。
切换可能会导致设备内的功耗和噪声增加;
然而，这些将是相当微不足道的。如果有必要将接收器的引脚保持在已知的逻辑状态，输入可以通过上拉至VCCO进行直流偏置，并下拉至GND。设计目标是获得
输入差分电压达到确保已知逻辑电平处于IBUFDS输出的电平，同时仍确保输入引脚的信号完整性良好。
您应选择上拉和下拉电阻，以便在未驱动的情况下，差分输入电压大于数据手册中差分输入标准的最小VID。
然后，您应该执行IBIS或Spice仿真，输入以所需的工作频率驱动，以确保仍满足输入规范，并确保输入端具有良好的信号完整性。
--------------------------------------------------
---------------------------------------------请将帖子标记为
如果提供的信息能够回答您的问题/解决您的问题，请“接受为解决方案”。给予您认为有用的帖子。



以下为原文

If the logical state of the differential receiver's pins is not important when they left un-driven (e.g., if input registers have been disabled), you do not need to do anything. The receiver's output might toggle if enough noise is present; however, this will not damage the device. The toggling might lead to increased power consumption and noise within the device; however, these will be fairly insignificant.

If it is necessary to keep the receiver's pins at a known logical state, the inputs can be DC-biased with a pull-up to VCCO and pull-down to GND.
The design goal is to get the input differential voltage to a level that ensure a known logic level is at the IBUFDS output while still ensuring that the signal integrity is good at the input pin.

You should select the Pull-up and Pulldown resistors such that in the undriven case the differential input voltage is greater than minimum VID for the differential input standard in the data sheet.

You should then perform an IBIS or Spice simulation with the input being driven at the desired operating frequency to ensure that the input specifications are still met and that there is good signal integrity at the input.-----------------------------------------------------------------------------------------------
Please mark the post as "Accept as solution" if the information provided answers your query/resolves your issue.

Give Kudos to a post which you think is helpful.

嗨，谢谢你的回答。
我想避免使用外部元件。我试图在P侧设置内部上拉，并在差分端接的同时在N侧设置内部下拉，ISE发出有关信号完整性的警告。
有这方面的经验吗？
这种情况是否得到IBIS模拟的支持？



以下为原文

Hi, thanks for your answer.
I'd like to avoid external components.I tried to set an internal pullup on the P side, and internal pulldown on the N side at the same time as the differential termination, ISE issues a warning about signal integrity.
Any experience on this ? Is this case supported by IBIS simulation ?
 
 

p，
可以在任何SI模拟器中对此进行建模（添加最小值电阻并查看它如何影响信号）。
一般来说，即使是1K欧姆的上拉或下拉也不会影响操作。
Austin Lesea主要工程师Xilinx San Jose



以下为原文

p,
 
One can model this in any SI simulator (add the min value resistors and see how it affects the signals).
 
Generally speaking, even a pullup or pulldown of 1K ohms will probably not affect the operation.
 
 
 
 
Austin Lesea
Principal Engineer
Xilinx San Jose