如何知道FPGA输出端口的电平信号上升和下降时间？

在无负载（开路引脚）的情况下，相同电压和IO标准的上升/下降时间相同，相同类型的FPGA具有相同的速率。
如果我们通过PCB轨道连接负载，则结果上升/下降时间会根据负载而变化。
IBIS模拟是找到合成上升/下降时间的好方法。
要进行IBIS模拟，用户必须从XILINX网站下载相关的IBIS模型。
然后，用户必须通过采用特定的FPGA IBIS模型，连接IC IBIS模型和传输线（TL）模型，在SI工具中进行SI（信号完整性）仿真。
为此，SI模拟XILINX为每个设备提供了IBIS模型。
以下链接提供了适用于Xilinx器件的IBIS模型：http：//www.xilinx.com/support/download/index.htm
_______________________________________________如果有助于解决您的查询，请将此帖子标记为“接受为解决方案”。
因此，它将有助于其他论坛用户直接参考答案。如果您认为该信息有用且面向答复，请给予此帖子称赞。
在原帖中查看解决方案



以下为原文

With no load (Open pin) the rise/ fall times are same for same voltage & IO standards with same slew rate in the same type FPGA .
 
If we connect load through PCB track then the resultant rise/ fall times changes based on load. IBIS simulations is good workaround to find resultant rise/fall times.
 
To do  IBIS simulations user has to download relevant IBIS model from XILINX web site. Then user has to conduct SI (Signal Integrity) simulations in SI tools by taking that particular FPGA IBIS model, interfacing IC IBIS model and Transmission Line (TL) models . To do that SI simulations XILINX provided IBIS model for each device.  
 

• The IBIS models for Xilinx devices available in the following link 
  http://www.xilinx.com/support/download/index.htm  
  

 
________________________________________________

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View solution in original post

这些将取决于驱动信号走线/导线上的特性阻抗，电容和所有其他负载。一旦您了解所有这些，您就可以使用Xilinx提供的IBIS模型来计算（通常通过合适的仿真工具）什么
上升/下降时间是。
------------------------------------------“如果它不起作用
模拟，它不会在板上工作。“



以下为原文

These will depend on the characteristic impedence, capacitance, and all other loads on the signal trace/wire being driven.

Once you know all those, you can use the IBIS models that Xilinx provide to calculate (usually via a suitable simulation tool) what the rise/fall times are.

------------------------------------------
"If it don't work in simulation, it won't work on the board."

谢谢
对不起，我没有表达清楚;
如果我们的示波器具有无限宽频谱，我们可以直接将其连接到FPGA芯片的输出端口而无需负载。
示波器屏幕上出现的上升和下降时间是多少？
10ns的？
YHM



以下为原文

Thank you
 
I am sorry that I did not express clearly;
 
If we have an oscilloscope with Infinitely wide spectrum, we connect it to the output port of FPGA chip directly without load.
 
What is the rising and falling time that dispayed on the oscilloscope screen?    <1ns ,1ns-10nns or >10ns?
 
yhm

yhm写道：
谢谢
对不起，我没有表达清楚;
如果我们的示波器具有无限宽频谱，我们可以直接将其连接到FPGA芯片的输出端口而无需负载。
示波器屏幕上出现的上升和下降时间是多少？
10ns的？
YHM
应小于10 ns。
当然，对于未端接的线，线长度很重要。
----------------------------是的，我这样做是为了谋生。



以下为原文

yhm wrote:
Thank you
 
I am sorry that I did not express clearly;
 
If we have an oscilloscope with Infinitely wide spectrum, we connect it to the output port of FPGA chip directly without load.
 
What is the rising and falling time that dispayed on the oscilloscope screen?    <1ns ,1ns-10nns or >10ns?
 
yhm

Should be less than 10 ns. Of course, with an unterminated line, the line length matters.
----------------------------Yes, I do this for a living.

我会注意到，示波器探头/输入将（错误地）终止FPGA输出，从而服从量子“观察者效应”。
------------------------------------------“如果它不起作用
模拟，它不会在板上工作。“



以下为原文

I would note that the oscilloscope probe/input will (mis-)terminate the FPGA output, thereby obeying the quantum 'observer effect'.

------------------------------------------
"If it don't work in simulation, it won't work on the board."

如果您在没有负载的情况下直接将其连接到FPGA芯片的输出端口，并且如果您的探头是理想的，那么上升/下降时间几乎要高于您在ucf文件中定义的IO标准的转换速率。
。
仅供参考：IBIS模拟是您在电路板上估算/下降时间的最佳选择
_______________________________________________如果有助于解决您的查询，请将此帖子标记为“接受为解决方案”。
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以下为原文

If you connect it to the output port of FPGA chip directly without load and if your probe is ideal then the rise/fall times  is  little above the slew rates of IO standards which you defined in your ucf file. .
 
FYI: The IBIS simulations is best option to estimate rise/fall times on your board
________________________________________________

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谢谢您的回答。
从您的答案来看，我认为不同FPGA芯片的上升/下降时间相似。
换句话说，上升/下降时间取决于IO标准的转换速率以外的负载。
我的理解是对的？
谢谢！
YHM



以下为原文

Thank you for your answer.
 
From your answer,I think that the rise/fall times is similar for different FPGA chips.
 
In other words, the rise/fall times depends on the load except the slew rates of IO standards.
 
My understanding is correct?
 
Thank you!
 
yhm

在无负载（开路引脚）的情况下，相同电压和IO标准的上升/下降时间相同，相同类型的FPGA具有相同的速率。
如果我们通过PCB轨道连接负载，则结果上升/下降时间会根据负载而变化。
IBIS模拟是找到合成上升/下降时间的好方法。
要进行IBIS模拟，用户必须从XILINX网站下载相关的IBIS模型。
然后，用户必须通过采用特定的FPGA IBIS模型，连接IC IBIS模型和传输线（TL）模型，在SI工具中进行SI（信号完整性）仿真。
为此，SI模拟XILINX为每个设备提供了IBIS模型。
以下链接提供了适用于Xilinx器件的IBIS模型：http：//www.xilinx.com/support/download/index.htm
_______________________________________________如果有助于解决您的查询，请将此帖子标记为“接受为解决方案”。
因此，它将有助于其他论坛用户直接参考答案。如果您认为该信息有用且面向答复，请给予此帖子称赞。



以下为原文

With no load (Open pin) the rise/ fall times are same for same voltage & IO standards with same slew rate in the same type FPGA .
 
If we connect load through PCB track then the resultant rise/ fall times changes based on load. IBIS simulations is good workaround to find resultant rise/fall times.
 
To do  IBIS simulations user has to download relevant IBIS model from XILINX web site. Then user has to conduct SI (Signal Integrity) simulations in SI tools by taking that particular FPGA IBIS model, interfacing IC IBIS model and Transmission Line (TL) models . To do that SI simulations XILINX provided IBIS model for each device.  
 

• The IBIS models for Xilinx devices available in the following link 
  http://www.xilinx.com/support/download/index.htm  
  

 
________________________________________________

Please mark this post as an "Accept as solution" in case if it helped to resolve your query. So that it will help to other forum users to directly refer to the answer.

Give kudos to this post in case if you think the information is useful and reply oriented.

什么是你使用的simalation工具，谢谢。我想模拟信号完整性，但我以前从未做过。谢谢。
Michael ------------------------------------------感谢上帝，我遇到了FPGA
.------------------------------------------



以下为原文

what's the simalation tool you use,thanks.
I want to simulate the signal integrity,but I have never done it before.Thanks.Michael

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Thanks for god,I meet FPGA.
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