斯巴达3E XC3S100E写入内存问题

你能发布你的代码吗？
这听起来像你没有看到
读取正确时钟周期的数据。
递增模式你
如果Block RAM以默认模式运行，则会发生描述
写入优先，你正在查看第一个读取数据
地址稳定的两个周期。
这实际上会给你
由于直写逻辑，从先前地址写入数据
在块RAM中。
读取数据实际上在第二次有效
在有效地址的两个周期中，您需要进行添加
组合（没有时钟延迟）。
问候，
的Gabor
-  Gabor
在原帖中查看解决方案



以下为原文

Can you post your code?  It sounds to me like you are not looking at the
read data on the correct clock cycle.  The incrementing pattern you
describe would happen if the Block RAM is running in the default mode
of write-first, and you are looking at the read data on the first of the
two cycles that your address is stable.  This would actually give you the
write data from the previous address due to the write-through logic
in the block RAM.  The read data is actually valid during the second
of the two cycles of valid address, so your addition needs to happen
combinatorially (without a clock delay).
 
Regards,
Gabor
-- GaborView solution in original post

如果您正在使用Block RAM，则需要注意内存上有一个寄存器
读取输出，以便在应用地址后，旧数据在循环中出现。
然后
你的添加需要在你写回内存的同一个时钟周期内发生。
所以
你有一个时钟周期：输出时间的内存加上组合
加法器的延迟和写入内存的设置时间。
如果您发现需要管道
除了满足时序（我不确定你在25 ns时做），那么你需要更多的时钟周期
或者你需要改变你的方法来交替连续的读写周期
数据输入。
我在Virtex 5上使用后一种方法在200 MHz，所以它不应该
Spartan 3在40 MHz时出现的任何问题。
我仍然对你的陈述感到有点困惑
“写入比双倍时钟周期花费更多时间”
这是真实硬件还是您的测试平台在行为期间向您展示这一点
模拟？
问候，
的Gabor
-  Gabor



以下为原文

If you are using block RAM, you need to be aware that the memory has a register on the
read output so the old data comes out on the cycle after you apply the address.  Then
your addition needs to happen in the same clock cycle you write the memory back.  So
you have in one clock cycle: the clock to output time of the memory plus the combinatorial
delay of your adder and the setup time to write memory.  If you find that you need to pipeline
the addition to meet timing (I'm not sure you do at 25 ns) then you would need more clock cycles
or you need to change your approach to interleave read and write cycles from successive
data inputs.  I have used the latter approach on Virtex 5 at 200 MHz, so it shouldn't have
any problems in Spartan 3 at 40 MHz.  Still I'm a bit confused on your statement
 "the write takes me more time then the double rate clock period"
Is this in the real hardware or is your testbench showing you this during behavioral
simulation?
 
Regards,
Gabor
-- Gabor

首先感谢您的时间和知识
作为你的问题的答案，我在测试台上看到了这一点（行为模仿）
我认为你是对的，在40Mhz中实现它不应该是一个问题
（我用xilinxdefinitions检查）
问候
埃菲



以下为原文

first thank you for your time and knowledge
 
as an answer to your question i ment that i see that in test bench (behavioral imulation)
 
i think that you are right and it not supposed to be a problem to implement that in 40Mhz
 
( i check that with xilinx definitions )
 
regards
 
 Efi 

你能发布你的代码吗？
这听起来像你没有看到
读取正确时钟周期的数据。
递增模式你
如果Block RAM以默认模式运行，则会发生描述
写入优先，你正在查看第一个读取数据
地址稳定的两个周期。
这实际上会给你
由于直写逻辑，从先前地址写入数据
在块RAM中。
读取数据实际上在第二次有效
在有效地址的两个周期中，您需要进行添加
组合（没有时钟延迟）。
问候，
的Gabor
-  Gabor



以下为原文

Can you post your code?  It sounds to me like you are not looking at the
read data on the correct clock cycle.  The incrementing pattern you
describe would happen if the Block RAM is running in the default mode
of write-first, and you are looking at the read data on the first of the
two cycles that your address is stable.  This would actually give you the
write data from the previous address due to the write-through logic
in the block RAM.  The read data is actually valid during the second
of the two cycles of valid address, so your addition needs to happen
combinatorially (without a clock delay).
 
Regards,
Gabor
-- Gabor

只想对你的时间说谢谢
你可以看到问题已经解决了。谢谢



以下为原文

just want to say TNX for your time
 
as you can see the problem was solved  THANKS

我（kamal）想要在fpga上做我的主要项目。我的clg提供了xilinx spartan 3e xcs100e fpga board..so请帮我决定项目的主题..我的电子邮件ID是kamal.bhugra7@gmail.com



以下为原文

i (kamal) want to make my major project on fpga..my clg provided me  xilinx spartan 3e xcs100e fpga board..so kindly help me in deciding topic of the project..
my email id is kamal.bhugra7@gmail.com