请问我是否必须考虑将信号路由到输出引脚的规则？

大家好，
我刚刚经历了一个我根本无法解释的奇怪行为。
我的设置如下：我有两个FPGA，一个是控制FPGA的Spartan3和一个进行计算的Virtex5。
两者都只通过总线连接。
Spartan通过该总线向Virtex提供时钟信号。
一切都很完美。
现在我想把这个来自Spartan的时钟信号输出到我的电路板的输出引脚，这样我就可以在示波器上看到它以获得更好的方向，而且没有任何工作了，我得到了错误的结果。
此外，Virtex消耗的功率比以前更多。
看起来驱动信号的能力来自Virtex通过总线而不是来自它应该来自的Spartan，如果它有任何意义......
可能有人对这种行为有解释吗？
我是否必须考虑将信号路由到输出引脚的规则？
干杯，
Sobsen



以下为原文

Hi all,

I just experienced a strange behavior I cannot explain at all. My setup is the following: I have two FPGAs, a Spartan3 which is the controlling FPGA and a Virtex5 which does computations. Both are connected through a bus only. The Spartan provides a clock signal over this bus to the Virtex. Everything works perfectly.
Now I wanted to output this clock signal from the Spartan to an output pin of my board so I can see it on the oscilloscope for better orientation, and nothing is working anymore and I get wrong results. Furthermore, the Virtex is consuming way more power than before. It seems the power to drive the signal is taken from the Virtex over the bus instead from the Spartan where it's supposed to come from, if it makes any sense...

May somebody have an explanation for this behavior? Do I have to consider some rules to route a signal to the output pins?

Cheers,
Sobsen